Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Proceedings - 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2012

Volumn , Issue , 2012, Pages 457-464

  Wang, Chifeng ^a   Bagherzadeh, Nader ^a  

^a University of California at Irvine   (United States)

Author keywords

Congestion aware; Interconnection network; Network on Chip (NoC); Quality of Service (QoS)

Indexed keywords

ADAPTIVE ROUTING; CONGESTION-AWARE; COST EVALUATIONS; DIFFERENT SERVICES; DYNAMIC ARBITRATION; HIGH THROUGHPUT; IMPLEMENTATION COST; NETWORK ON CHIP; NETWORK TRANSMISSION; NETWORK-ON-CHIP ARCHITECTURES; QOS REQUIREMENTS; ROUTER ARCHITECTURE; TRAFFIC LOADS; TRAFFIC PATTERN;

COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS; NETWORK ARCHITECTURE; QUALITY OF SERVICE; SERVERS; VLSI CIRCUITS;

TRAFFIC CONGESTION;

EID: 84862127772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2012.20     Document Type: Conference Paper

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