Congestion-aware network-on-chip router architecture

Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010

Volumn , Issue , 2010, Pages 137-144

  Wang, Chifeng ^a   Hu, Wen Hsiang ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Congestion aware; Interconnection network; Multi processor system on chip (MPSoC); Network on chip (NoC)

Indexed keywords

ADAPTIVE ROUTING; CONGESTION CONTROL; CONGESTION-AWARE; COST EVALUATIONS; IMPLEMENTATION COST; LATENCY PERFORMANCE; MULTI PROCESSOR SYSTEM ON CHIPS; NETWORK ACTIVITIES; NETWORK ON CHIP; NETWORK THROUGHPUT; NETWORK TRANSMISSION; NETWORK-ON-CHIP ARCHITECTURES; ROUTER ARCHITECTURE; SIMULATION RESULT; TRAFFIC LOAD DISTRIBUTION; TRAFFIC PATTERN;

ADAPTIVE CONTROL SYSTEMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER GRAPHICS; INTERCONNECTION NETWORKS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; ROUTERS; SERVERS; THROUGHPUT; TRAFFIC CONGESTION; VLSI CIRCUITS;

COMPUTER ARCHITECTURE;

EID: 78650094827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CADS.2010.5623552     Document Type: Conference Paper

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