Area and power-efficient innovative congestion-aware Network-on-Chip architecture

Journal of Systems Architecture

Volumn 57, Issue 1, 2011, Pages 24-38

  Wang, Chifeng ^a   Hu, Wen Hsiang ^a   Lee, Seung Eun ^b   Bagherzadeh, Nader ^a  

^a University of California at Irvine   (United States)

^b Seoul National University of Science and Technology   (South Korea)

Author keywords

Area efficient; Congestion aware; Interconnection network; Network on Chip (NoC); Power efficient

Indexed keywords

ADAPTIVENESS; AREA EFFICIENT; CONGESTION-AWARE; CONGESTION-AWARE ROUTING; HIGH THROUGHPUT; IMPLEMENTATION COST; LARGE BUFFER; MESH NETWORK; NETWORK ACTIVITIES; NETWORK ON CHIP; NETWORK TRANSMISSION; NETWORK-ON-CHIP ARCHITECTURES; POWER CONSUMPTION; POWER EFFICIENT; POWER-EFFICIENT SOLUTIONS; PROPOSED ARCHITECTURES; SIMULATION RESULT; SWITCHING TECHNIQUES; TRAFFIC LOADS; TRAFFIC PATTERN;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; INTERCONNECTION NETWORKS; MESH NETWORKING; NETWORK PERFORMANCE; PACKET SWITCHING; ROUTERS; ROUTING ALGORITHMS; SERVERS; TRAFFIC CONGESTION; VLSI CIRCUITS;

NETWORK ARCHITECTURE;

EID: 78650271572     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2010.10.009     Document Type: Article

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