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Volumn 4128 LNCS, Issue , 2006, Pages 884-895

Towards a cost-effective interconnection network architecture with QoS and congestion management support

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CONGESTION CONTROL (COMMUNICATION); COST EFFECTIVENESS; QUALITY OF SERVICE; QUEUEING NETWORKS;

EID: 33750027442     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11823285_93     Document Type: Conference Paper
Times cited : (4)

References (16)
  • 8
    • 0026883882 scopus 로고
    • Dynamically-allocated multi-queue buffers for vlsi communication switches
    • Tamir, Y., Frazier, G.: Dynamically-allocated multi-queue buffers for vlsi communication switches. IEEE Transactions on Computers 41 (1992)
    • (1992) IEEE Transactions on Computers , vol.41
    • Tamir, Y.1    Frazier, G.2
  • 14
    • 33750005431 scopus 로고    scopus 로고
    • Design of a 32×32 variable-packet-size buffered crossbar switch chip
    • Inst. of Computer Science, FORTH
    • Simos, D.: Design of a 32×32 variable-packet-size buffered crossbar switch chip. Technical Report FORTH-ICS/TR-339, Inst. of Computer Science, FORTH (2004) http://archvlsi.ics.forth.gr/bufxbar/.
    • (2004) Technical Report , vol.FORTH-ICS-TR-339
    • Simos, D.1
  • 15
    • 84941162206 scopus 로고    scopus 로고
    • ESi-RAM/2P™ Two-port register file SRAM
    • Virtual Silicon Technology, Inc.: eSi-RAM/2P™ Two-port register file SRAM. Data Sheet (2004)
    • (2004) Data Sheet


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.