On design and analysis of a feasible Network-on-Chip (NoC) architecture

Proceedings - International Conference on Information Technology-New Generations, ITNG 2007

Volumn , Issue , 2007, Pages 1033-1038

  Bahn, Jun Ho ^a   Lee, Seung Eun ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; MICROPROCESSOR CHIPS; PROBLEM SOLVING; ROUTING ALGORITHMS; VLSI CIRCUITS;

COMPARING SIMULATION; MIMD MESSAGE PASSING ARCHITECTURE; PACKET DEFINITION;

NETWORK ARCHITECTURE;

EID: 34548126965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITNG.2007.139     Document Type: Conference Paper

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