Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1361-1366

  Chen, Chen ^a   Lee, W Scott ^a   Parsa, Roozbeh ^a   Chong, Soogine ^a   Provine, J ^a   Watt, Jeff ^b   Howe, Roger T ^a   Wong, H S Philip ^a   Mitra, Subhasish ^a  

^a Stanford University   (United States)

^b ALTERA CORPORATION   (United States)

Author keywords

CMOS NEM FPGA; FPGA routing; Half select programming; NEM relay

Indexed keywords

CMOS CIRCUITS; DESIGN TECHNIQUE; DYNAMIC POWER; ENERGY EFFICIENT; FUNCTIONAL OPERATION; IN-FIELD; LEAKAGE POWER; PROGRAMMABILITY; REDUCTION IN AREA; ROUTING BUFFERS; ROUTING SWITCHES;

CMOS INTEGRATED CIRCUITS; DESIGN; EXHIBITIONS; TIME SWITCHES;

ELECTRIC PROPERTIES;

EID: 84862112740     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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