Architecture and performance evaluation of 3D CMOS-NEM FPGA

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2011, Pages

  Dong, Chen ^a   Chen, Chen ^b   Mitra, Subhasish ^b   Chen, Deming ^a  

^a University of Illinois at Urbana Champaign   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D STACKING; ARCHITECTURE AND PERFORMANCE; BUILT-IN FEATURE; CMOS COMPONENTS; CONFIGURABLE LOGIC BLOCKS; CONNECTION BLOCK; DELAY REDUCTION; DIRECT LINKS; LOCAL COMMUNICATIONS; LOOK UP TABLE; NANO-ELECTROMECHANICAL; PERFORMANCE GAIN; PLACEMENT AND ROUTING; RECONFIGURABLE ARCHITECTURE; SWITCH BLOCKS; TWO-STACK; UNIQUE FEATURES;

ARCHITECTURE; ELECTRIC POWER SYSTEM INTERCONNECTION; TABLE LOOKUP;

THREE DIMENSIONAL;

EID: 84863173710     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SLIP.2011.6135428     Document Type: Conference Paper

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