cFPGA: CNT emerging memory-based FPGA

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 1444-1447

  Wang, Wei ^a   Jing, Tom T ^a   Butcher, Brian ^a  

^a STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS DEVICES; CMOS TRANSISTORS; DYNAMIC POWER REDUCTION; EFFICIENT ARCHITECTURE; FPGA CIRCUITS; HYBRID FPGA; NANORELAYS; PERFORMANCE IMPROVEMENTS; QUANTUM RESISTANCE; RECONFIGURABLE ARCHITECTURE; ROUTING SWITCHES; SIGNAL PATHS; SIGNAL TRANSMISSION; STANDBY POWER; SWITCHING ELEMENTS;

CARBON NANOTUBES;

FABRICS;

EID: 77955999478     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537322     Document Type: Conference Paper

References (9)

1. T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C. L. Cheung, C. M. Lieber, "Carbon nanotube-based nonvolatile random access memory for molecular computing", Science, vol. 289, pp.94-97, 2000.
2. Y. Zhou, S. Thekkel, and S. Bhunia, "Low power FPGA design using hybrid CMOS-NEMS approach", in: Proc. of ISLPED, pp.14-19, 2007.
3. S. Eachempati, A. Nieuwoudt, A. Gayasen, N.Vijaykrishnan, and Y. Massoud, "Assessing carbon nanotube bundle interconnect for future FPGA architectures", in: Proc. of DATE, pp.1-6, 2007.
4. C. Dong, S. Chilstedt, and D. Chen, "FPCNA: A field programmable carbon nanotube array", in: Proc. of ACM FPGA, pp.161-170, 2009.
5. S.W. Lee, et al., "A three-terminal carbon nanorelay", Nano Lett., vol. 4, no. 10, pp.2027-2030, 2004.
6. B. Kaul, et al., "Electromechanical carbon nanotube switches for highfrequency applications", Nano Lett., vol. 6, no. 5, pp.942-947, 2006.
7. S. Bhunia, M. Tabib-Azar, and D. Saab, "Ultralow-power adaptive system architecture using complementary nano-electromechanical carbon nanotube switches", in: Proc. of IEEE/ACM ASP-DAC, pp.383- 390, 2007.
8. R.S. Chakraborty, S. Narasimhan, and S. Bhunia, "Hybridization of CMOS with CNT-Based nano electromechanical switch for low leakage and robust circuit design using nanoscaled CMOS devices", IEEE Trans. on CAS I, vol. 54, no. 11, pp.2480-2488, 2007.
9. G. Lemieux and D. Lewis, "Circuit design of routing switches", in: Porc. of FPGA, pp.452-455, 2002.