Design and reliability of a micro-relay technology for zero-standby-power digital logic applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Kam, Hei ^a   Pott, Vincent ^a   Nathanael, Rhesa ^a   Jeon, Jaeseok ^a   Alon, Elad ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; ANSYS SIMULATION; CMOS COMPATIBLE; CMOS DEVICES; CMOS TECHNOLOGY; DESIGN TECHNIQUE; DIGITAL LOGIC APPLICATIONS; ENERGY SAVING; MICRO-ELECTRO-MECHANICAL; MICRO-RELAY; ON-STATE RESISTANCE; RELAY OPERATIONS; SUPPLY VOLTAGES; SURFACE ADHESION; SWITCHING BEHAVIORS; SWITCHING CYCLES; TEMPERATURE RANGE; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; DIGITAL DEVICES; ELECTRON DEVICES; ENERGY CONSERVATION; MATHEMATICAL MODELS; MODELS;

COMPUTER SIMULATION;

EID: 77952415045     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424218     Document Type: Conference Paper

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