-
1
-
-
64949182836
-
Novel functional logic circuits based on 3-D emerging memory cells
-
San Francisco, CA
-
S. Fujita and T. H. Lee, "Novel functional logic circuits based on 3-D emerging memory cells," in Proc. 1st 3-D Architectures for Semiconductor Integr. Packag. Conf., San Francisco, CA, 2003, pp. 77-92.
-
(2003)
Proc. 1st 3-D Architectures for Semiconductor Integr. Packag. Conf
, pp. 77-92
-
-
Fujita, S.1
Lee, T.H.2
-
2
-
-
64949111010
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Novel architecture based on floating gate CNT-NEMS switches and its application to 3-D on-chip bus beyond CMOS architecture
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Anaheim
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S. Fujita, K. Abe, and T. H. Lee, "Novel architecture based on floating gate CNT-NEMS switches and its application to 3-D on-chip bus beyond CMOS architecture," in Proc. 8th NSTI Nanotechnology Conf. Trade Show, Anaheim, 2005, pp. 100-104.
-
(2005)
Proc. 8th NSTI Nanotechnology Conf. Trade Show
, pp. 100-104
-
-
Fujita, S.1
Abe, K.2
Lee, T.H.3
-
4
-
-
3142713373
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Effects of surface forces and phonon dissipation in a three-terminal nanorelay
-
Jul
-
L. M. Jonsson, T. Nord, J. M. Kinaret, and S. Viefers, "Effects of surface forces and phonon dissipation in a three-terminal nanorelay," J. Appl. Phys., vol. 96, no. 1, pp. 629-635, Jul. 2004.
-
(2004)
J. Appl. Phys
, vol.96
, Issue.1
, pp. 629-635
-
-
Jonsson, L.M.1
Nord, T.2
Kinaret, J.M.3
Viefers, S.4
-
5
-
-
7544219500
-
A three terminal carbon nanorelay
-
S. W. Lee, D. S. Lee, R. E. Morjan, S. H. Jhang, M. Sveningsson, U. A. Nerushev, Y. W. Dark, and E. E. B. Campbell, "A three terminal carbon nanorelay," Nanolett., vol. 4, no. 10, pp. 2027-2030, 2004.
-
(2004)
Nanolett
, vol.4
, Issue.10
, pp. 2027-2030
-
-
Lee, S.W.1
Lee, D.S.2
Morjan, R.E.3
Jhang, S.H.4
Sveningsson, M.5
Nerushev, U.A.6
Dark, Y.W.7
Campbell, E.E.B.8
-
6
-
-
18844366386
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A nonvolatile electromechanical memory utilizing fabrics of carbon nanotubes
-
Nov
-
J. W.Ward, M. Meinhold, B. M. Segal, J. Berg, R. Sen, R. Sivargan, D. K. Brock, and T. Rueckes, "A nonvolatile electromechanical memory utilizing fabrics of carbon nanotubes," in Proc. 5th Annual Non-Volatile Memory Technol. Symp., Nov. 2004, pp. 34-38.
-
(2004)
Proc. 5th Annual Non-Volatile Memory Technol. Symp
, pp. 34-38
-
-
Ward, J.W.1
Meinhold, M.2
Segal, B.M.3
Berg, J.4
Sen, R.5
Sivargan, R.6
Brock, D.K.7
Rueckes, T.8
-
8
-
-
2442653656
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Interconnect limits on gigascale integration in the 21st century
-
Mar
-
J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, "Interconnect limits on gigascale integration in the 21st century," Proc. IEEE, vol. 89, no. 3, pp. 305-324, Mar. 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.3
, pp. 305-324
-
-
Davis, J.A.1
Venkatesan, R.2
Kaloyeros, A.3
Beylansky, M.4
Souri, S.J.5
Banerjee, K.6
Saraswat, K.C.7
Rahman, A.8
Reif, R.9
Meindl, J.D.10
-
9
-
-
64949112934
-
-
ITRS Roadmap, Santa Clara, CA, Online].Available
-
ITRS Roadmap, International Technology Roadmap for Semiconductors, Santa Clara, CA, 2005 [Online].Available: http://www.public.itrs.net/Files/ 2003ITRS/Home2003.htm
-
(2005)
-
-
-
10
-
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34548848512
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Carbon nanotube transistor circuits: Circuit-level performance benchmarking and design options for living with imperfections
-
San Francisco
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J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra, and H.-S. P. Wong, "Carbon nanotube transistor circuits: Circuit-level performance benchmarking and design options for living with imperfections," in Tech. Dig. ISSCC, San Francisco, 2007.
-
(2007)
Tech. Dig. ISSCC
-
-
Deng, J.1
Patil, N.2
Ryu, K.3
Badmaev, A.4
Zhou, C.5
Mitra, S.6
Wong, H.-S.P.7
-
11
-
-
33746910456
-
-
A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. DiMilia, M. T. Robson, E. Duch, M. Farinelli, C.Wang, R. A. Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T. Kwietniak, C. D'Emic, J. Ott, A. M.Young, K. W. Guarini, and M. Ieong, Enabling SOIBased assembly technology for Three-Dimensional (3-D) Integrated Circuits (ICs), in Tech. Dig. IEDM, Washington, DC, 2005, pp. 363-366, For example:.
-
A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. DiMilia, M. T. Robson, E. Duch, M. Farinelli, C.Wang, R. A. Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T. Kwietniak, C. D'Emic, J. Ott, A. M.Young, K. W. Guarini, and M. Ieong, "Enabling SOIBased assembly technology for Three-Dimensional (3-D) Integrated Circuits (ICs)," in Tech. Dig. IEDM, Washington, DC, 2005, pp. 363-366, For example:.
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-
-
-
12
-
-
50149119548
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Novel design of threedimensional crossbar for future network on chip based on post-silicon devices
-
Lausanne, Switzerland
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K. Nomura, K. Abe, S. Fujita, and A. DeHon, "Novel design of threedimensional crossbar for future network on chip based on post-silicon devices," in Proc. 1st NanoNet Conf., Lausanne, Switzerland, 2006, pp. 4-8.
-
(2006)
Proc. 1st NanoNet Conf
, pp. 4-8
-
-
Nomura, K.1
Abe, K.2
Fujita, S.3
DeHon, A.4
-
14
-
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34548858682
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An 80-tile 1.28TFLOPS network-on-chip in 65-nm CMOS
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San Francisco, CA
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S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, and N. Borkar, "An 80-tile 1.28TFLOPS network-on-chip in 65-nm CMOS," in Tech. Dig. ISSCC, San Francisco, CA, 2007, no. 3-5.
-
(2007)
Tech. Dig. ISSCC
, Issue.3-5
-
-
Vangal, S.1
Howard, J.2
Ruhl, G.3
Dighe, S.4
Wilson, H.5
Tschanz, J.6
Finan, D.7
Iyer, P.8
Singh, A.9
Jacob, T.10
Jain, S.11
Venkataraman, S.12
Hoskote, Y.13
Borkar, N.14
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