A circuit and architecture codesign approach for a hybrid CMOSSTTRAM nonvolatile FPGA

IEEE Transactions on Nanotechnology

Volumn 10, Issue 3, 2011, Pages 385-394

  Paul, Somnath ^a   Mukhopadhyay, Saibal ^b   Bhunia, Swarup ^a  

^a Case Western Reserve University   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Emerging memory technologies; nonvolatile field programmable gate array (FPGA); Shannon decomposition; spin torque transfer RAM (STTRAM)

Indexed keywords

APPLICATION MAPPING; BENCHMARK CIRCUIT; CO-DESIGN APPROACH; CONFIGURABLE LOGIC BLOCKS; DESIGN CHALLENGES; DYNAMIC POWER; EMBEDDED MEMORY ARRAYS; FPGA DESIGN; HIGH INTEGRATION DENSITY; HYBRID FPGA; INTRINSIC PROPERTY; LOOK UP TABLE; LOW POWER; MEMORY TECHNOLOGY; NOISE MARGINS; NON-VOLATILE; NONVOLATILE FPGA; NONVOLATILITY; OPTIMIZATION TECHNIQUES; POWER REDUCTIONS; READ NOISE; READOUT POWER; RESEARCH EFFORTS; SHANNON DECOMPOSITION; SIMULATION RESULT; SPIN TORQUE; SPIN TORQUE TRANSFER RAM (STTRAM); STATIC POWER; STATIC-POWER DISSIPATION; SUPPLY GATING; VOLTAGE SENSING;

DELAY CIRCUITS; DESIGN; LOGIC GATES; MEMORY ARCHITECTURE; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79955917574     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2010.2041555     Document Type: Article

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