Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 27-38

  Miller, Timothy N ^a   Pan, Xiang ^a   Thomas, Renji ^a   Sedaghati, Naser ^a   Teodorescu, Radu ^a  

^a Ohio State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENT FREQUENCY; FREQUENCY VARIATION; GOVERNOR CONTROL; LOW VOLTAGES; LOW-VOLTAGE; MANY CORE; MAXIMUM FREQUENCY; MULTI-THREADED APPLICATION; ON CHIPS; PERFORMANCE IMPROVEMENTS; POWER CONSTRAINTS; POWER-SUPPLY RAILS; PROCESS VARIATION; REBALANCING; SUPPLY VOLTAGES; TIME SPENT;

COMPUTER ARCHITECTURE; GOVERNORS; SUPERCOMPUTERS; VALUE ENGINEERING;

BENCHMARKING;

EID: 84860352303     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6168942     Document Type: Conference Paper

References (39)

1. A. Bhattacharjee and M. Martonosi. Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. In International Symposium on Computer Architecture, pages 290-301, June 2009.
2. R. D. Blumofe and C. E. Leiserson. Scheduling multithreaded computations by work stealing. Journal of the ACM, 46:720-748, September 1999.
3. Q. Cai, J. González, R. Rakvic, G. Magklis, P. Chaparro, and A. González. Meeting points: Using thread criticality to adapt multicore hardware to parallel regions. In International Conference on Parallel Architectures and Compilation Techniques, pages 240-249, October 2008.
4. B. Calhoun and A. Chandrakasan. Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering. 41(1):238-245, January 2006.
5. A. Chandrakasan, D. Daly, D. Finchelstein, J. Kwong, Y. Ramadass, M. Sinangil, V. Sze, and N. Verma. Technologies for ultradynamic voltage scaling. Proceedings of the IEEE, 98(2):191-214, February 2010.
6. L. Chang, D. Frank, R. Montoye, S. Koester, B. Ji, P. Coteus, R. Dennard, and W. Haensch. Practical strategies for power-efficient computing technologies. Proceedings of the IEEE, 98(2):215-236, February 2010.
7. R. Dreslinski. Near Threshold Computing: From Single Core to Many-Core Energy Efficient Architectures. PhD thesis, The University of Michigan, 2011.
8. R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. Near-threshold computing: Reclaiming Moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2):253-266, February 2010.
9. R. G. Dreslinski, G. K. Chen, T. Mudge, D. Blaauw, D. Sylvester, and K. Flautner. Reconfigurable energy efficient near threshold cache architectures. In International Symposium on Microarchitecture, pages 459-470, December 2008.
10. A. Duran, J. Corbalán, and E. Ayguadé. Evaluation of OpenMP task scheduling strategies. In International Conference on OpenMP in a New Era of Parallelism, pages 100-110, May 2008.
11. H. R. Ghasemi, S. Draper, and N. S. Kim. Low-voltage on-chip cache architecture using heterogeneous cell sizes for multi-core processors. In IEEE International Symposium on High-Performance Computer Architecture, pages 38-49, February 2011.
12. Y. Guo, R. Barik, R. Raman, and V. Sarka. Work-first and help-first scheduling policies for async-finish task parallelism. In IEEE International Parallel and Distributed Processing Symposium, pages 1-12, May 2009.
13. S. Herbert and D. Marculescu. Mitigating the impact of variability on chip-multiprocessor power and performance. IEEE Transactions on Very Large Scale Integrated Systems, 17:1520-1533, October 2009.
14. E. Humenay, D. Tarjan, and K. Skadron. The impact of systematic process variations on symmetrical performance in chip multiprocessors. In Design, Automation and Test in Europe, April 2007.
15. Intel CoreTM i7 Processor. http://www.intel.com.
16. International Technology Roadmap for Semiconductors (2009).
17. H. Jiang and M. Marek-Sadowska. Power gating scheduling for power/ground noise reduction. In Design Automation Conference, pages 980-985, June 2008.
18. W. Kim, D. Brooks, and G.-Y. Wei. A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation. In International Solid-State Circuits Conference, pages 268-270, February 2011.
19. W. Kim, M. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. In IEEE International Symposium on High-Performance Computer Architecture, pages 123-134, February 2008.
20. S. Kulkarni, A. Srivastava, and D. Sylvester. A new algorithm for improved VDD assignment in low power dual VDD systems. In International Symposium on Low Power Electronics and Design, pages 200-205, May 2004.
21. N. Kurd, P. Mosalikanti, M. Neidengard, J. Douglas, and R. Kumar. Next generation Intel Core micro-architecture (Nehalem) clocking. IEEE Journal of Solid-State Circuits, 44(4):1121-1129, April 2009.
22. J. Leverich, M. Monchiero, V. Talwar, P. Ranganathan, and C. Kozyrakis. Power management of datacenter workloads using per-core power gating. IEEE Computer Architecture Letters, 8:48-51, July 2009.
23. J. Li, J. Martínez, and M. C. Huang. The thrifty barrier: Energy-aware synchronization in shared-memory multiprocessors. In IEEE International Symposium on High-Performance Computer Architecture, pages 14-24, February 2004.
24. X. Liang, G.-Y. Wei, and D. Brooks. ReVIVaL: A variation-tolerant architecture using voltage interpolation and variable latency. IEEE Micro, 29(1):127-138, 2009.
25. C. Liu, A. Sivasubramaniam, M. Kandemir, and M. J. Irwin. Exploiting barriers to optimize power consumption of CMPs. In IEEE International Parallel and Distributed Processing Symposium, pages 1-5, April 2005.
26. D. Markovic, C. Wang, L. Alarcon, T.-T. Liu, and J. Rabaey. Ultralow-power design in near-threshold region. Proceedings of the IEEE, 98(2):237-252, February 2010.
27. P. Maulik and D. Mercer. A DLL-based programmable clock multiplier in 0.18-um CMOS with -70 dBc reference spur. IEEE Journal of Solid-State Circuits, 42(8):1642-1648, August 2007. (Pubitemid 47171128)
28. R. McGowen, C. A. Poirier, C. Bostak, J. Ignowski, M. Millican, W. H. Parks, and S. Naffziger. Power and temperature control on a 90-nm Itanium family processor. IEEE Journal of Solid-State Circuits, 41(1):229-237, January 2006. (Pubitemid 43145980)
29. T. Miller, J. Dinan, R. Thomas, B. Adcock, and R. Teodorescu. Parichute: Generalized turbocode-based error correction for near-threshold caches. In International Symposium on Microarchitecture, pages 351-362, December 2010.
30. T. Miller, R. Thomas, and R. Teodorescu. Mitigating the effects of process variation in ultra-low voltage chip multiprocessors using dual supply voltages and half-speed stages. IEEE Computer Architecture Letters, 11(1), 2012.
31. K. K. Rangan, G.-Y. Wei, and D. Brooks. Thread motion: Fine-grained power management for multi-core systems. In International Symposium on Computer Architecture, pages 302-313, June 2009.
32. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, K. Strauss, S. Sarangi, P. Sack, and P. Montesinos. SESC Simulator, January 2005. http://sesc.sourceforge.net.
33. T. Saeki, M. Mitsuishi, H. Iwaki, and M. Tagishi. A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for clock on demand. IEEE Journal of Solid-State Circuits, 35(11):1581-1590, November 2000. (Pubitemid 32070550)
34. S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. VARIUS: A model of parameter variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing, 21(1):3-13, February 2008. (Pubitemid 351229812)
35. D. Shelepov, J. C. S. Alcaide, S. Jeffery, A. Fedorova, N. Perez, Z. F. Huang, S. Blagodurov, and V. Kumar. Hass: A scheduler for heterogeneous multicore systems. SIGOPS Operating Systems Review, 43(2):66-75, April 2009.
36. R. Teodorescu and J. Torrellas. Variation-aware application scheduling and power management for chip multiprocessors. In International Symposium on Computer Architecture, pages 363-374, June 2008.
37. J. Torrellas. Architectures for extreme-scale computing. IEEE Computer, 42:28-35, November 2009.
38. S. Vangal. A solar powered IA core? No way! Research@Intel, September 2011. http://blogs.intel.com/research/2011/09/ntvp.php.
39. B. Zhai, R. G. Dreslinski, D. Blaauw, T. Mudge, and D. Sylvester. Energy efficient near-threshold chip multi-processing. In International Symposium on Low Power Electronics and Design, pages 32-37, August 2007.