Power gating scheduling for power/ground noise reduction

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 980-985

  Jiang, Hailin ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

Power gating; Power supply noise; Scheduling

Indexed keywords

POWER GATING; POWER SUPPLY NOISE;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER TRANSMISSION; LEAKAGE CURRENTS; POWER GENERATION; WAKES;

SCHEDULING;

EID: 51549098641     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555962     Document Type: Conference Paper

References (10)

1. D. E. Goldberg, "Genetic and evolutionary algorithms come of age," Comm. of the ACM, vol 37, No. 3, March 1994, pp. 113-119.
2. A. Davoodi and A. Srivastava, "Wake-up protocols for controlling current surges in MTCMOS-based technology", in Proc. of Asia South Pacific Design Automation Conference, pp. 868-871, 2005.
3. S. Henzler and M. Eireiner, "Activation technique for sleep-transistor circuits for reduced power supply noise," in Proc. European Solid-State Circuits Conference, 2006, pp. 102-105.
4. S. Kim, S. V. Kosonocky, and D. R. Knebel, "Understanding and minimizing ground bounce during mode transition of power-gating structures," in Proc. International Symposium on Low Power Electronics and Design, 2003, pp. 22-25.
5. W. D. Lam, C. K. Koh, and C. A. Tsao, "Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy," in Proc. of International Symposium on Quality Electronic Design, pp. 327-332, 2003.
6. S. Mutoh and et al, "A 1V power supply high-speed digital circuit technology with multi threshold voltage CMOS," IEEE J. of Solid-State Circuit, vol. 30, No. 8, August 1995, pp. 847-854.
7. A. Ramalingam, A. Devgan, and D. Z. Pan, "Walk-up scheduling in MTCOMS circuits using successive relaxation to minimize ground bounce", J. of Low Power Electronics, Vol. 3, No. 1, pp. 1-8, 2007.
8. A. Vittal, H. Ha, F. Brewer, and M. Marek-Sadowska, "Clock-skew optimization for ground bounce control," in Proc. of International Conference on Computer Aided Design, pp. 395-399, 1996.
9. P. Vuillod, L. Benini, A. Bogliolo, and G. De. Micheli, "Clock-skew optimization for peak current reduction," in Proc. of International Symposium on Low Power Electronics and Design, pp. 265-270, 1996.
10. MCNC Benchmarks. [online]. Available: http://www.cbl.ncsu.edu/pub/ Benchmark divs/