Next generation Intel® core micro-architecture (Nehalem) clocking

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 4, 2009, Pages 1121-1129

  Kurd, Nasser ^a   Mosalikanti, Praveen ^a   Neidengard, Mark ^a   Douglas, Jonathan ^a   Kumar, Rajesh ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Delay locked loop (DLL); IA; Intel QuickPath; Interconnect; Memory controller; Phase locked loop (PLL)

Indexed keywords

COMPUTER ARCHITECTURE; DELAY CIRCUITS; JITTER; SPURIOUS SIGNAL NOISE;

DELAY-LOCKED LOOP (DLL); IA; INTERCONNECT; MEMORY CONTROLLER; PHASE-LOCKED LOOP (PLL);

PHASE LOCKED LOOPS;

EID: 63449130377     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2014023     Document Type: Conference Paper

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