1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for 'clock on demand'

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1581-1590

  Saeki, Takanori ^a,b   Mitsuishi, Masafumi ^a,c   Iwaki, Hiroaki ^a,d   Tagishi, Mitsuaki ^a,e  

^a NEC CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c TOKYO UNIVERSITY OF SCIENCE   (Japan)

^d TOKYO DENKI UNIVERSITY   (Japan)

^e KANAGAWA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC INVERTERS; ERROR CORRECTION; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; MOS DEVICES; PHASE LOCKED LOOPS; SHORT CIRCUIT CURRENTS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK ON DEMAND; CLOCK SYNCHRONIZED DELAY; DELAY LOCKED LOOP CLOCK MULTIPLIER; DIRECT CLOCK CYCLE; MULTIPHASE CLOCK MULTIPLIER; SHORT CIRCUIT CURRENT SUPPRESSION INTERPOLATOR;

TIMING CIRCUITS;

EID: 0034317650     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881203     Document Type: Article

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