A 12b 75MS/s pipelined ADC using open-loop residue amplification

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Murmann, Boris ^a   Boser, Bernhard E ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; BANDWIDTH; BIT ERROR RATE; BUFFER AMPLIFIERS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS; SIGNAL NOISE MEASUREMENT; SIGNAL TO NOISE RATIO; STATISTICAL METHODS; TABLE LOOKUP;

BINARY PSEUDO RANDOM NUMBER GENERATOR; CONVERTER FRONTEND; DIGITAL BACKGROUD CALIBRATION TECHNIQUE; OPEN LOOP RESIDUE AMPLIFICATION; PRECISION AMPLIFIERS;

ANALOG TO DIGITAL CONVERSION;

EID: 0037630797     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. D. Kelly et al., "A 3V 14b 75MSPS CMOS ADC with 85dB SFDR at Nyquist," ISSCC Dig. Tech. Papers, pp. 143-44, Feb. 2001.
2. A. Karanicolas et al., "A 15-b 1-MSample/s Digitally Self-Calibrated Pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.
3. I. E. Opris et al., "A Single-Ended 12-bit 20 MSample/s Self-Calibrating Pipeline A/D Converter," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1898-1903, Dec. 1998.