A 4.4 pJ/Access 80 MHz, 128 kbit variability resilient sram with multi-sized sense amplifier redundancy

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 10, 2011, Pages 2416-2430

  Sharma, Vibhu ^a,b   Cosemans, Stefan ^a,c   Ashouei, Maryam ^b   Huisken, Jos ^b   Catthoor, Francky ^a,c   Dehaene, Wim ^a,c  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b HOLST CENTRE   (Netherlands)

^c IMEC   (Belgium)

Author keywords

Charge recycling; gated read buffer; Multi Sized SA; SRAM; ultra low energy; WRITE masking

Indexed keywords

6T-SRAM; BITLINES; CALIBRATION TECHNIQUES; CHARGE RECYCLING; ENERGY EFFICIENT; ENERGY REDUCTION; GATED READ BUFFER; LOW POWER TECHNIQUES; LOW SWING; MULTI-SIZED SA; SENSE AMPLIFIER; ULTRA LOW ENERGY; WIRELESS SENSOR;

CALIBRATION; ENERGY UTILIZATION; LOW POWER ELECTRONICS; REDUNDANCY; STATIC RANDOM ACCESS STORAGE;

ENERGY EFFICIENCY;

EID: 80053640415     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2159056     Document Type: Conference Paper

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