A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Volumn , Issue , 2009, Pages 225-228

  Sinangil, Mahmut E ^a   Verma, Naveen ^a   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY ARCHITECTURE; MINIMAL AREA; ON-CHIP REFERENCES; PSEUDO DIFFERENTIAL; REFERENCE VOLTAGES; SENSE AMPLIFIER; T-TESTS; TEST CHIPS; ULTRA-LOW POWER; VOLTAGE-SCALING;

STATIC RANDOM ACCESS STORAGE;

EID: 76249108649     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357219     Document Type: Conference Paper

References (9)

1. L. Chang and et al, "Stable SRAM. Cell Design for the 32nm Node and Beyond," in Symposium on VLSI Circuits (VLSI) Digest of Technical Papers, June 2005, pp. 128-129.
2. R. Joshi and et al., "6.6+ GHz Low VmIn, read and half select disturbfree 1.2Mb SRAM," in Symposium on VLSI Circuits (VLSI) Digest of Technical Papers, June 2007, pp. 250-251.
3. N. Verma and A. Chandrakasan, "A 65nm 8t sub-vt sram. employing sense-amplifier redundancy," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb. 2006, pp. 328-329.
4. Y. Morita and et al., "An Area-Conscious Low-Voltage-Oriented 8TSRAM Design under DVS Environment," in Symposium on VLSI Circuits (VLSI) Digest of Technical Papers, June 2007, pp. 256-257.
5. I. J. Chang, J. Kim, S. P. Park, and K. Roy, "A 32kb 10T Subthreshold SRAM Array with Bit-interleaving and Differential Read Scheme in 90nm CMOS," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb. 2008, pp. 388-389.
6. A. Kawasumi. and et al., "A Single-Power-Supply 0.7V 1GHz. 45nm SRAM with An Asymmetrical. Unit-β-ratio Memory Cell," in IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, Feb. 2008, pp. 382-383.
7. K. Kushida and et al., "A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme," in Symposium on VLSI Circuits ( VLSI) Digest of Technical Papers, June 2008, pp. 46-47.
8. M. Yamaoka, K. Osada, and T. Kawahara, "A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis," in IEEE European Solid-Slate Circuits Conference (ESSCIRC) Digest of Technical Papers, Sept. 2008, pp. 286-289.
9. S. Coscmans, W. Dehaene, and F. Catthoor, "A 3.6pJ/access 480MHz, 128Kbit on-chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability," in IEEE European Solid-State Circuits Conference (ESSCIRC) Digest of Technical Papers, Sept. 2008, pp. 278-281.