A low-power SRAM using hierarchical bit line and local sense amplifiers

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 6, 2005, Pages 1366-1376

  Yang, Byung Do ^a   Kim, Lee Sup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Hierarchical bit line; Local sense amplifier; Low power; Low swing; SRAM; Write

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS; VLSI CIRCUITS; WAVEFORM ANALYSIS;

HIERARCHICAL BIT LINE; LOCAL SENSE AMPLIFIERS; LOW-POWER SRAM; WRITE AMPLIFIERS;

STATIC RANDOM ACCESS STORAGE;

EID: 20444436009     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848032     Document Type: Article

References (7)

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