A 3.6 pJ/access 480 MHz, 128 kb on-chip SRAM with 850 MHz boost mode in 90 nm CMOS with tunable sense amplifiers

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 7, 2009, Pages 2065-2077

  Cosemans, Stefan ^a   Dehaene, Wim ^a   Catthoor, Francky ^a,b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b IMEC   (Belgium)

Author keywords

Bit line hierarchy; Calibrated timing; Dynamic cell stability; Embedded memory; Low power; Selective voltage scaling; Sense amplifier calibration; SRAM; Variability aware design

Indexed keywords

BIT LINE HIERARCHY; CALIBRATED TIMING; EMBEDDED MEMORY; LOW-POWER; SELECTIVE VOLTAGE SCALING; SENSE AMPLIFIER CALIBRATION; SRAM; VARIABILITY-AWARE DESIGN;

CALIBRATION; CELL MEMBRANES; ELECTRIC POTENTIAL; TIME MEASUREMENT; TIMING CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 67651165361     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2021925     Document Type: Article

References (16)

1. N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8 T subthreshold SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
2. B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200 mV 6 T SRAM in 0.13 m CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 332-333.
3. Y. Wang et al., "A 1.1 GHz 12 μ A/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 172-179, Jan. 2008.
4. J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, T. Kono, D. Nelson, O. Takahashi, S. Tokito, O. Torreiter, O. Wagner, and D. Wendel, "Implementation of the CELL broadband engine in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 V," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 322-323.
5. K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, "A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113-121, Jan. 2006.
6. S. Cosemans, W. Dehaene, and F. Catthoor, "A low power embedded SRAM for wireless applications," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1607-1617, July 2007.
7. S. Cosemans, W. Dehaene, and F. Catthoor, "A 3.6 pJ/access 480 MHz, 128 kb on-chip SRAM with 850 MHz boost mode in 90 nm CMOS with tunable sense amplifiers to cope with variability," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2008, pp. 278-281.
8. T. Doom, J. Ter Maten, J. Croon, A. Di Bucchianico, and O. Wittich, "Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2008, pp. 230-233.
9. B. D. Jang and L. S. Kim, "A low-power SRAM using hierarchical bit line and local sense amplifiers," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, Jun. 2005.
10. G. Kim, M. K. Kim, B. S. Chang, and W. Kim, "A low-voltage, low-power CMOS delay element," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966-971, Jul. 1996.
11. J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, and H. E. Maes, "An easy-to-use mismatch model for the MOS transistor," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1056-1064, Aug. 2002.
12. Y. Watanabe, N. Nakamura, and S. Watanabe, "Offset compensating bit-line sensing scheme for high density DRAM's," IEEE J. Solid-State Circuits, vol. 29, no. 1, pp. 9-13, Jan. 1994.
13. N. Verma and A. P. Chandrakasan, "A high-density 45 nm SRAM using small-signal non-strobed regenerative sensing," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 380-381.
14. E. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAMs," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525-536, Apr. 1991.
15. P. Geens and W. Dehaene, "A dual port dual width 90 nm SRAM with guaranteed data retention at minimal standby supply voltage," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2008, pp. 290-293.
16. M. Sinangil, N. Verma, and A. Chandrakasan, "A reconfigurable 65 nm SRAM achieving voltage scalability from 0.25-1.2 V and performance scalability from 20 kHz-200 MHz," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2008, pp. 282-285.