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Volumn 42, Issue 7, 2007, Pages 1607-1617

A low-power embedded SRAM for wireless applications

Author keywords

Embedded memory; Low power; SRAM

Indexed keywords

LOW POWER;

EID: 34347226224     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.896693     Document Type: Conference Paper
Times cited : (29)

References (17)
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    • Geens, P.1    Dehaene, W.2
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    • Dynamic zero-sensitivity scheme for low-power cache memories
    • Jul.-Aug
    • Y. Chang and F. Lai, "Dynamic zero-sensitivity scheme for low-power cache memories," IEEE Micro, vol. 25, no. 4, pp. 20-32, Jul.-Aug. 2005.
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    • A low-power SRAM using hierarchical bit line and local sense amplifiers
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    • B. D.Yang and L. S. Kim, "A low-power SRAM using hierarchical bit line and local sense amplifiers," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, Jun. 2005.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.