Analog and digital circuit design in 65 nm CMOS: End of the road?

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 37-42

  Gielen, Georges ^a   Dehaene, Wim ^a   Christie, Phillip ^b   Draxelmayr, Dieter ^c   Janssens, Edmond ^d   Maex, Karen ^e   Vucurevich, Ted ^f  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

^c Infineon   (Austria)

^d STMICROELECTRONICS   (Belgium)

^e IMEC   (Belgium)

^f Cadence   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; NANOTECHNOLOGY; PROCESS CONTROL;

EMBEDDED ANALOG BLOCK; LEAKAGE POWER; PROCESS VARIABILITY; SIGNAL INTEGRITY;

SYSTEMS ANALYSIS;

EID: 33646915471     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.64     Document Type: Conference Paper

References (13)

1. "International Technology Roadmap for Semiconductors 2003," http://public.itrs.net.
2. nd edition)", Prentice Hall, 2002.
3. D. Frank, "Parameter variations in sub-100nm technology," ISSCC microprocessor workshop, San Fransico, February 2004.
4. D. Frank, P. Wong, "Simulation of Stochastic Doping Effects in Si MOSFETs," IWCE, 2000.
5. T. Kobayashi et al., "Self-adjusting threshold -voltage scheme (SATS) for low-voltage high-speed operation,"proc. CICC, pp.271-274, May 1994.
6. T. Sakurai, "Adaptive Circuit Techniques for Managing Variations," ISSCC microprocessor workshop, San Fransico, February 2004.
7. P. Kinget, M. Steyaert, "Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits," proc. CICC, pp. 333-336, May 1996.
8. S. Director, P. Feldmann, K. Krishna, "Statistical integrated circuit design," IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, pp. 193-202, March 1993.
9. G. Gielen, R. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits," Proceedings of the IEEE, Vol. 88, No. 12, pp. 1825-1854, December 2000.
10. G. Van der Plas, et al., "AMGIE - A synthesis environment for CMOS analog integrated circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, pp. 1037-1058, September 2001.
11. S. Donnay, G. Gielen (editors), "Analysis and reduction techniques for substrate noise coupling in mixed-signal integrated circuits," European Mixed-Signal Initiative for Electronic System Design, Kluwer Academic Publishers, 2003.
12. D. Leenaerts, G. Gielen, R. Rutenbar, "CAD solutions and outstanding challenges for mixed-signal and RF IC design," proceedings ICCAD, pp. 270-277, November 2001.
13. M. van Heijningen, M. Badaroglu, S. Donnay, G. Gielen, H. De Man, "Substrate noise generation in complex digital systems: efficient modeling and simulaton methodology and experimental verification," IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1065-1072, August 2002.