Low-power SRAM design using half-swing pulse-mode techniques

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1659-1670

  Mai, Kenneth W ^a,c,d   Mori, Toshihiko ^a,b,c,e   Amrutur, Bharadwaj S ^a,c,f   Ho, Ron ^a,c,d,g   Wilburn, Bennett ^a,c,h   Horowitz, Mark A ^a,c,i,j   Fukushi, Isao ^b,k   Izawa, Tetsuo ^b   Mitarai, Shin ^b  

^a Stanford University   (United States)

^b FUJITSU LABORATORIES LTD   (Japan)

^c STANFORD UNIVERSITY   (United States)

^d Stanford University ^*  (United States)

^e OSAKA UNIVERSITY   (Japan)

^f INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^g INTEL CORPORATION   (United States)

^h HEWLETT PACKARD COMPANY   (United States)

ⁱ MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^j RAMBUS INC   (United States)

^k TOHOKU UNIVERSITY   (Japan)

more..

Author keywords

Low power; Low voltage; Memory architecture; Self timing; SRAM chips

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

HALF-SWING PULSE-MODE TECHNIQUES; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0032202489     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726555     Document Type: Article

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