Low power SRAM with boost driver generating pulsed word line voltage for sub-1V operation

Journal of Computers

Volumn 3, Issue 5, 2008, Pages 34-40

  Iijima, Masaaki ^a   Seto, Kayoko ^a   Numa, Masahiro ^a   Tada, Akira ^b   Ipposhi, Takashi ^b  

^a KOBE UNIVERSITY   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Circuit methodology; Low power; Low voltage; PD S0I; SRAM; Vth variation

Indexed keywords

LOW POWER ELECTRONICS;

CAPACITIVE COUPLINGS; DESIGN CHALLENGES; LOW POWER; LOW SUPPLY VOLTAGES; LOW VOLTAGES; PROCESS VARIATION; SRAM MEMORY CELLS; SUPPLY VOLTAGES;

STATIC RANDOM ACCESS STORAGE;

EID: 76449103117     PISSN: 1796203X     EISSN: None     Source Type: Journal    
DOI: 10.4304/jcp.3.5.34-40     Document Type: Article

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