A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7™ processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 344-345

  Pille, Juergen ^a   Wendel, Dieter ^a   Wagner, Otto ^a   Sautter, Rolf ^a   Penth, Wolfgang ^a   Froehnel, Thomas ^a   Buettner, Stefan ^a   Torreiter, Otto ^a   Eckert, Martin ^a   Paredes, Jose ^b   Hrusecky, David ^b   Ray, David ^b   Canada, Miles ^b  

^a IBM   (Germany)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL CIRCUITRY; DATA CACHES; DENSE ARRAYS; INDIVIDUAL CONTROL; MICROPROCESSOR CORE; MULTI-PORT; MULTI-THREADING; OUT OF ORDER; READ OPERATION; SOI TECHNOLOGY; WRITE OPERATIONS;

CACHE MEMORY; SILICON ON INSULATOR TECHNOLOGY;

MICROPROCESSOR CHIPS;

EID: 77952167003     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433849     Document Type: Conference Paper

References (5)

1. R. Kalla et al, "POWER7™: IBM's Next Generation POWER Microprocessor", Hot Chips 2009.
2. D. Wendel et al, "The Implementation of POWER7™, an 8-Core, 4 Threads per Core, High End Server Processor in 45nm SOI Technology", ISSCC 2010.
3. J. Davis et al, "A 5.6GHz 64kB Dual-Read Data Cache for the POWER6 Processor", ISSCC 2006.
4. J. Pille et al, "Implementation of the CELL Broadband Engine™ in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V", ISSCC 2007.
5. K. Zhang et al, "The Scaling of Data Sensing for High Speed Cache Designs in Sub-0.18μm Technologies", VLSI Circuits Symposium 2000.