Analyzing static and dynamic write margin for nanometer SRAMs

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 129-134

  Wang, Jiajing ^a   Nalam, Satyanand ^a   Calhoun, Benton H ^a  

^a University of Virginia   (United States)

Author keywords

Dynamic noise margin; Reliability; SRAM; Static noise margin; Variation; VCCmin; Write margin

Indexed keywords

CAPACITANCE; DESIGN; ELECTRIC LOAD SHEDDING; LOGIC DESIGN; LOW POWER ELECTRONICS; POWER ELECTRONICS; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

DYNAMIC NOISE MARGIN; SRAM; STATIC NOISE MARGIN; VARIATION; VCCMIN; WRITE MARGIN;

STABILITY CRITERIA;

EID: 57549111680     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393954     Document Type: Conference Paper

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