-
1
-
-
37749013850
-
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
-
L. Chang, Y. Nakamura, R. K. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. H. Gebara, K. B. Agarwal, D. J. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, "A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS," in 2007 IEEE Symposium on VLSI Circuits, 2007, pp. 252-253.
-
(2007)
2007 IEEE Symposium on VLSI Circuits
, pp. 252-253
-
-
Chang, L.1
Nakamura, Y.2
Montoye, R.K.3
Sawada, J.4
Martin, A.K.5
Kinoshita, K.6
Gebara, F.H.7
Agarwal, K.B.8
Acharyya, D.J.9
Haensch, W.10
Hosokawa, K.11
Jamsek, D.12
-
2
-
-
39749154813
-
6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM
-
R. Joshi, R. Houle, K. Batson, D. Rodko, P. Patel, W. Huott, R. Franch, Y. Chan, D. Plass, S. Wilson, and P. Wang, "6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM," in 2007 IEEE Symposium on VLSI Circuits, 2007, pp. 250-251.
-
(2007)
2007 IEEE Symposium on VLSI Circuits
, pp. 250-251
-
-
Joshi, R.1
Houle, R.2
Batson, K.3
Rodko, D.4
Patel, P.5
Huott, W.6
Franch, R.7
Chan, Y.8
Plass, D.9
Wilson, S.10
Wang, P.11
-
3
-
-
34548830136
-
A sub-200mV 6T SRAM in 130nm CMOS
-
B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, "A sub-200mV 6T SRAM in 130nm CMOS," Int. Solid-State Circuits Conf, 2007.
-
(2007)
Int. Solid-State Circuits Conf
-
-
Zhai, B.1
Blaauw, D.2
Sylvester, D.3
Hanson, S.4
-
4
-
-
30844457740
-
A novel five-transistor (5T) sram cell for high performance cache
-
M. Wieckowski and M. Margala, "A novel five-transistor (5T) sram cell for high performance cache," in The IEEE International SOC Conference, 2005, pp. 101-102.
-
(2005)
The IEEE International SOC Conference
, pp. 101-102
-
-
Wieckowski, M.1
Margala, M.2
-
5
-
-
51749104874
-
Portless SRAM - A High-Performance Alternative to the 6T Methodolgy
-
November
-
M. Wieckowski, S. Patil, and M. Margala, "Portless SRAM - A High-Performance Alternative to the 6T Methodolgy," IEEE Journal of Solid-State Circuits, vol. 42, November 2007.
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
-
-
Wieckowski, M.1
Patil, S.2
Margala, M.3
-
6
-
-
0015100002
-
MOSFET memory circuits
-
L. M. Terman, "MOSFET memory circuits," Proceedings of the IEEE, vol. 59, pp. 1044-1058, 1971.
-
(1971)
Proceedings of the IEEE
, vol.59
, pp. 1044-1058
-
-
Terman, L.M.1
-
7
-
-
48349091667
-
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM
-
I. Masaaki, K. Masayuki, N. Masahiro, T. Akira, and I. Takashi, "Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM," in 20th International Conference on VLSI Design, 2007, pp. 609-614.
-
(2007)
20th International Conference on VLSI Design
, pp. 609-614
-
-
Masaaki, I.1
Masayuki, K.2
Masahiro, N.3
Akira, T.4
Takashi, I.5
-
8
-
-
0347528892
-
Ultralow-power SRAM technology
-
September/November
-
R. W. Mann, W. W. Abadeer, M. J. Breitwisch, O. Bula, J. S. Brown, and B. C. Colwill, "Ultralow-power SRAM technology," IBM Journal of Research and Development, vol. 47, pp. 553-566, September/November 2003.
-
(2003)
IBM Journal of Research and Development
, vol.47
, pp. 553-566
-
-
Mann, R.W.1
Abadeer, W.W.2
Breitwisch, M.J.3
Bula, O.4
Brown, J.S.5
Colwill, B.C.6
|