Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2009, Pages 709-712

  Nalam, Satyanand ^a   Calhoun, Benton H ^a  

^a University of Virginia   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

5T SRAM; BITCELL; BULK CMOS; READ STABILITY; WRITE MARGIN;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 74049150723     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280733     Document Type: Conference Paper

References (12)

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