-
1
-
-
0029288557
-
Trends in low-power RAM circuit technologies
-
Itoh K., Sasaki K., and Nakagome Y. Trends in low-power RAM circuit technologies. Proceedings of the IEEE 83 4 (1995) 524-543
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.4
, pp. 524-543
-
-
Itoh, K.1
Sasaki, K.2
Nakagome, Y.3
-
3
-
-
39749158643
-
Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit
-
K. Takeda, et al., Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit, in: IEEE International Solid-State Circuits Conference (2006) 2602-2611.
-
(2006)
IEEE International Solid-State Circuits Conference
, pp. 2602-2611
-
-
Takeda, K.1
-
4
-
-
31344451652
-
A 3 GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply
-
Zhang K., et al. A 3 GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply. IEEE Journal of Solid-State Circuits 41 1 (2006) 146-151
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.1
, pp. 146-151
-
-
Zhang, K.1
-
5
-
-
2942659548
-
0.4 V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme
-
Yamaoka M., Osada K., and Ishibashi K. 0.4 V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE Journal of Solid-State Circuits 39 6 (2004) 934-940
-
(2004)
IEEE Journal of Solid-State Circuits
, vol.39
, Issue.6
, pp. 934-940
-
-
Yamaoka, M.1
Osada, K.2
Ishibashi, K.3
-
6
-
-
33947694725
-
An SRAM design in 65 nm technology node featuring read and write-assist circuits to expand operating voltage
-
Pilo H., et al. An SRAM design in 65 nm technology node featuring read and write-assist circuits to expand operating voltage. IEEE Journal of Solid-State Circuits 42 4 (2007) 813-819
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.4
, pp. 813-819
-
-
Pilo, H.1
-
7
-
-
34548274890
-
On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology
-
Lai F.-S., and Lee C.-F. On-chip voltage down converter to improve SRAM read/write margin and static power for sub-nano CMOS technology. IEEE Journal of Solid-State Circuits 42 9 (2007) 2061-2070
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.9
, pp. 2061-2070
-
-
Lai, F.-S.1
Lee, C.-F.2
-
8
-
-
33644642661
-
90 nm process-variation adaptive embedded SRAM modules with power-line-floating write technique
-
Yamaoka M., et al. 90 nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE Journal of Solid-State Circuits 41 3 (2006) 705-711
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.3
, pp. 705-711
-
-
Yamaoka, M.1
-
10
-
-
33947613119
-
A 65 nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits
-
Ohbayashi S., et al. A 65 nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. IEEE Journal of Solid-State Circuits 42 4 (2007) 820-829
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.4
, pp. 820-829
-
-
Ohbayashi, S.1
-
11
-
-
33644640188
-
Stable SRAM cell design for the 32 nm node and beyond
-
L. Chang, et al., Stable SRAM cell design for the 32 nm node and beyond, in: Symposium on VLSI Technology (2005) 128-129.
-
(2005)
Symposium on VLSI Technology
, pp. 128-129
-
-
Chang, L.1
-
12
-
-
31344473488
-
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications
-
Takeda K., et al. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE Journal of Solid-State Circuits 41 1 (2006) 113-121
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.1
, pp. 113-121
-
-
Takeda, K.1
-
13
-
-
85008054031
-
A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy
-
Verma N., and Chandrakasan A.P. A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy. IEEE Journal of Solid-State Circuits 43 1 (2008) 141-149
-
(2008)
IEEE Journal of Solid-State Circuits
, vol.43
, Issue.1
, pp. 141-149
-
-
Verma, N.1
Chandrakasan, A.P.2
-
15
-
-
0032138640
-
A step-down boosted-wordline scheme for 1 V battery-operated fast SRAM's
-
Morimura H., and Shibata N. A step-down boosted-wordline scheme for 1 V battery-operated fast SRAM's. IEEE Journal of Solid-State Circuits 33 8 (1998) 1220-1227
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.33
, Issue.8
, pp. 1220-1227
-
-
Morimura, H.1
Shibata, N.2
-
16
-
-
0033169552
-
Optimization of wordline booster circuits for low-voltage flash memories
-
Tanzawa T., and Atsumi S. Optimization of wordline booster circuits for low-voltage flash memories. IEEE Journal of Solid-State Circuits 34 8 (1999) 1091-1098
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.34
, Issue.8
, pp. 1091-1098
-
-
Tanzawa, T.1
Atsumi, S.2
|