Application-aware topology reconfiguration for on-chip networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 11, 2011, Pages 2010-2022

  Modarressi, Mehdi ^a   Tavakkol, Arash ^b   Sarbazi Azad, Hamid ^a,b  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b INSTITUTE FOR RESEARCH IN FUNDAMENTAL SCIENCES IPM   (Iran)

Author keywords

Application specific systems on chip (SoCs); multi application based design; networks on chip (NoC); performance; power consumption; reconfigurable systems

Indexed keywords

ARCHITECTURAL ATTRIBUTES; CHIP MULTIPROCESSOR; MULTI CORE; MULTIPLE APPLICATIONS; NETWORK LATENCIES; NETWORK MAPPING; NETWORKS ON CHIPS; NEW APPLICATIONS; NOC ARCHITECTURES; ON-CHIP NETWORKS; OPTIMIZATION METHOD; PERFORMANCE; RE-CONFIGURABLE; RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE SYSTEMS; RUNNING APPLICATIONS; SYSTEM ON CHIPS; SYSTEMS ON CHIPS; TRAFFIC PATTERN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; OPTIMIZATION; STRUCTURAL DESIGN; TOPOLOGY;

ROUTERS;

EID: 80052879424     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2066586     Document Type: Article

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