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Volumn , Issue , 2006, Pages 4163-4166

Network-on-chip link analysis under power and performance constraints

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; ROUTERS; TELECOMMUNICATION LINKS;

EID: 34547352779     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (20)

References (15)
  • 1
    • 16244392403 scopus 로고    scopus 로고
    • SILENT: Serialized low energy transmission coding for on-chip interconnection networks
    • 7-11 Nov
    • K. Lee, S.-J. Lee, and H.-J. Yoo, "SILENT: serialized low energy transmission coding for on-chip interconnection networks," in IEEE/ACM International Conference on Computer Aided Design, 7-11 Nov. 2004, pp. 448-451.
    • (2004) IEEE/ACM International Conference on Computer Aided Design , pp. 448-451
    • Lee, K.1    Lee, S.-J.2    Yoo, H.-J.3
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini and G. D. Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    Micheli, G.D.2
  • 6
    • 0345666024 scopus 로고    scopus 로고
    • Interconnect modeling and optimization in deep sub-micron technologies,
    • Ph.D. dissertation, Massachusetts Institute of Technology
    • P. P. P. Sotiriadis, "Interconnect modeling and optimization in deep sub-micron technologies," Ph.D. dissertation, Massachusetts Institute of Technology, 2002.
    • (2002)
    • Sotiriadis, P.P.P.1
  • 7
    • 23744468720 scopus 로고    scopus 로고
    • N. Sridhara, S.R.; Shanbhag, Coding for system-on-chip networks: a unified framework, IEEE Transactions on VLSI Systems, 13, no. 6, pp. 655 - 667, Jun. 2005.
    • N. Sridhara, S.R.; Shanbhag, "Coding for system-on-chip networks: a unified framework," IEEE Transactions on VLSI Systems, vol. 13, no. 6, pp. 655 - 667, Jun. 2005.
  • 12
    • 1842582494 scopus 로고    scopus 로고
    • Reliable and efficient system-on-chip design
    • Mar
    • N. Shanbhag, "Reliable and efficient system-on-chip design," Computer, vol. 37, no. 3, pp. 42-50, Mar. 2004.
    • (2004) Computer , vol.37 , Issue.3 , pp. 42-50
    • Shanbhag, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.