-
1
-
-
16244392403
-
SILENT: Serialized low energy transmission coding for on-chip interconnection networks
-
7-11 Nov
-
K. Lee, S.-J. Lee, and H.-J. Yoo, "SILENT: serialized low energy transmission coding for on-chip interconnection networks," in IEEE/ACM International Conference on Computer Aided Design, 7-11 Nov. 2004, pp. 448-451.
-
(2004)
IEEE/ACM International Conference on Computer Aided Design
, pp. 448-451
-
-
Lee, K.1
Lee, S.-J.2
Yoo, H.-J.3
-
2
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
Jan
-
L. Benini and G. D. Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
6
-
-
0345666024
-
Interconnect modeling and optimization in deep sub-micron technologies,
-
Ph.D. dissertation, Massachusetts Institute of Technology
-
P. P. P. Sotiriadis, "Interconnect modeling and optimization in deep sub-micron technologies," Ph.D. dissertation, Massachusetts Institute of Technology, 2002.
-
(2002)
-
-
Sotiriadis, P.P.P.1
-
7
-
-
23744468720
-
-
N. Sridhara, S.R.; Shanbhag, Coding for system-on-chip networks: a unified framework, IEEE Transactions on VLSI Systems, 13, no. 6, pp. 655 - 667, Jun. 2005.
-
N. Sridhara, S.R.; Shanbhag, "Coding for system-on-chip networks: a unified framework," IEEE Transactions on VLSI Systems, vol. 13, no. 6, pp. 655 - 667, Jun. 2005.
-
-
-
-
9
-
-
13444257797
-
CDMA-based network-on-chip architecture
-
6-9 Dec
-
D. Kim, M. Kim, and G. E. Sobelman, "CDMA-based network-on-chip architecture," in Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems, vol. 1, 6-9 Dec. 2004, pp. 137-140.
-
(2004)
Proc. of the IEEE Asia-Pacific Conference on Circuits and Systems
, vol.1
, pp. 137-140
-
-
Kim, D.1
Kim, M.2
Sobelman, G.E.3
-
10
-
-
0034820186
-
Power Efficient Inter-Module Communication for Digit-Serial DSP Architecture In Deep-Submicron Technology
-
22-24 May
-
I. Dhaou, E. Dubrova, and H. Tenhunen, "Power Efficient Inter-Module Communication for Digit-Serial DSP Architecture In Deep-Submicron Technology," in Proc. of the 31st IEEE International Symposium on Multiple-Valued Logic, 22-24 May 2001, pp. 61-66.
-
(2001)
Proc. of the 31st IEEE International Symposium on Multiple-Valued Logic
, pp. 61-66
-
-
Dhaou, I.1
Dubrova, E.2
Tenhunen, H.3
-
11
-
-
0041633582
-
A Survey of Techniques for Energy Efficient On-Chip Communication
-
2-6 Jun
-
V. Raghunathan, M. Srivastava, and R. Gupta, "A Survey of Techniques for Energy Efficient On-Chip Communication," in Proc. of the Design Automation Conference, 2-6 Jun. 2003, pp. 900 - 905.
-
(2003)
Proc. of the Design Automation Conference
, pp. 900-905
-
-
Raghunathan, V.1
Srivastava, M.2
Gupta, R.3
-
12
-
-
1842582494
-
Reliable and efficient system-on-chip design
-
Mar
-
N. Shanbhag, "Reliable and efficient system-on-chip design," Computer, vol. 37, no. 3, pp. 42-50, Mar. 2004.
-
(2004)
Computer
, vol.37
, Issue.3
, pp. 42-50
-
-
Shanbhag, N.1
-
13
-
-
0038419502
-
A global wire planning scheme for Network-on-Chip
-
25-28 May
-
J. Liu, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, "A global wire planning scheme for Network-on-Chip," in Proc. of the International Symposium on Circuits and Systems, vol. 4, 25-28 May 2003, pp. 25-28.
-
(2003)
Proc. of the International Symposium on Circuits and Systems
, vol.4
, pp. 25-28
-
-
Liu, J.1
Zheng, L.-R.2
Pamunuwa, D.3
Tenhunen, H.4
-
15
-
-
0038494696
-
Optimal global interconnects for GSI
-
Apr
-
A. Naeemi, R. Venkatesan, and J. Meindl, "Optimal global interconnects for GSI," IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 980-987, Apr. 2003.
-
(2003)
IEEE Transactions on Electron Devices
, vol.50
, Issue.4
, pp. 980-987
-
-
Naeemi, A.1
Venkatesan, R.2
Meindl, J.3
|