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Volumn , Issue , 2007, Pages 417-422

Power-aware mapping for reconfigurable NoC architectures

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; ELECTRIC PROPERTIES; MESH GENERATION; TOPOLOGY; WIRELESS NETWORKS;

EID: 52949130231     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2007.4601933     Document Type: Conference Paper
Times cited : (36)

References (19)
  • 2
    • 27644494723 scopus 로고    scopus 로고
    • Key Research Problems in NoC Design: A Holistic Perspective
    • Jersey City, NJ
    • U. Y. Ogras, J. Hu, R. Marculescu, "Key Research Problems in NoC Design: A Holistic Perspective", Proc. CODES+ISSS, Jersey City, NJ, 2005.
    • (2005) Proc. CODES+ISSS
    • Ogras, U.Y.1    Hu, J.2    Marculescu, R.3
  • 3
    • 33751395684 scopus 로고    scopus 로고
    • Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion
    • San Jose
    • U. Y. Ogras, R. Marculescu, "Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion", in IEEE/ACM Intl. Conf. on Computer Aided Design, San Jose, 2005.
    • (2005) IEEE/ACM Intl. Conf. on Computer Aided Design
    • Ogras, U.Y.1    Marculescu, R.2
  • 5
    • 16244409520 scopus 로고    scopus 로고
    • Multi-Objective Mapping for Mesh-based NoC Architectures
    • G. Ascia, V. Catania, and M. Palesi, "Multi-Objective Mapping for Mesh-based NoC Architectures," in. ISSS-CODES, 2004, pp. 182-187.
    • (2004) ISSS-CODES , pp. 182-187
    • Ascia, G.1    Catania, V.2    Palesi, M.3
  • 7
    • 17644417172 scopus 로고    scopus 로고
    • Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures
    • K. Srinivasan, K. S. Chama, and G. Konjevod, "Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures," in ICCD, 2004, pp. 422-429.
    • (2004) ICCD , pp. 422-429
    • Srinivasan, K.1    Chama, K.S.2    Konjevod, G.3
  • 13
    • 36349012734 scopus 로고    scopus 로고
    • A Detailed Architectural-level Power Model for Router Buffers, Crossbars and Arbiters
    • Technical report, Princeton University
    • H. Wang, "A Detailed Architectural-level Power Model for Router Buffers, Crossbars and Arbiters", Technical report, Princeton University, 2004.
    • (2004)
    • Wang, H.1
  • 17
    • 27144481574 scopus 로고    scopus 로고
    • G.Ascia, V. Catania, and M Palesi, An Evolutionary Approach to Network-on-Chip Mapping Problem, in The IEEE Congress on Evolutionary Computation, 2005, pp.112-119.
    • G.Ascia, V. Catania, and M Palesi, "An Evolutionary Approach to Network-on-Chip Mapping Problem," in The IEEE Congress on Evolutionary Computation, 2005, pp.112-119.
  • 18
    • 33746590812 scopus 로고    scopus 로고
    • Linear Programming Based Techniques for Synthesis of Network-on-Chip Achitectures
    • K. Srinvasan, K. Chatha, and G. Konjevod "Linear Programming Based Techniques for Synthesis of Network-on-Chip Achitectures", IEEE Tran. on VLSI, Vol. 14, No. 4, 2006, pp. 407-420.
    • (2006) IEEE Tran. on VLSI , vol.14 , Issue.4 , pp. 407-420
    • Srinvasan, K.1    Chatha, K.2    Konjevod, G.3
  • 19
    • 51849152734 scopus 로고    scopus 로고
    • NoC link analysis under power and performance constraints
    • Greece
    • M. Kim, D. Kim, and E. Sobelman, "NoC link analysis under power and performance constraints" ISCAS, Greece, 2006.
    • (2006) ISCAS
    • Kim, M.1    Kim, D.2    Sobelman, E.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.