-
2
-
-
27644494723
-
Key Research Problems in NoC Design: A Holistic Perspective
-
Jersey City, NJ
-
U. Y. Ogras, J. Hu, R. Marculescu, "Key Research Problems in NoC Design: A Holistic Perspective", Proc. CODES+ISSS, Jersey City, NJ, 2005.
-
(2005)
Proc. CODES+ISSS
-
-
Ogras, U.Y.1
Hu, J.2
Marculescu, R.3
-
3
-
-
33751395684
-
Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion
-
San Jose
-
U. Y. Ogras, R. Marculescu, "Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion", in IEEE/ACM Intl. Conf. on Computer Aided Design, San Jose, 2005.
-
(2005)
IEEE/ACM Intl. Conf. on Computer Aided Design
-
-
Ogras, U.Y.1
Marculescu, R.2
-
4
-
-
16444383201
-
Energy- and Performance-Aware Mapping for Regular NoC Architectures
-
J. Hu, R. Marculescu, "Energy- and Performance-Aware Mapping for Regular NoC Architectures", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.24, No.4, 2005.
-
(2005)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.4
-
-
Hu, J.1
Marculescu, R.2
-
5
-
-
16244409520
-
Multi-Objective Mapping for Mesh-based NoC Architectures
-
G. Ascia, V. Catania, and M. Palesi, "Multi-Objective Mapping for Mesh-based NoC Architectures," in. ISSS-CODES, 2004, pp. 182-187.
-
(2004)
ISSS-CODES
, pp. 182-187
-
-
Ascia, G.1
Catania, V.2
Palesi, M.3
-
7
-
-
17644417172
-
Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures
-
K. Srinivasan, K. S. Chama, and G. Konjevod, "Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures," in ICCD, 2004, pp. 422-429.
-
(2004)
ICCD
, pp. 422-429
-
-
Srinivasan, K.1
Chama, K.S.2
Konjevod, G.3
-
8
-
-
33746910637
-
Mapping and Configuration Methods for Multi-Use-Case Networks on Chips
-
S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, "Mapping and Configuration Methods for Multi-Use-Case Networks on Chips", Asia and South Pacific Design Automation Conference - ASP-DAC, 2006, pp. 146-151.
-
(2006)
Asia and South Pacific Design Automation Conference - ASP-DAC
, pp. 146-151
-
-
Murali, S.1
Coenen, M.2
Radulescu, A.3
Goossens, K.4
De Micheli, G.5
-
9
-
-
34047123275
-
A Methodology for Mapping Multiple Use Cases onto Networks on Chips
-
S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, "A Methodology for Mapping Multiple Use Cases onto Networks on Chips," Design Automation and Test in Europe (DATE), 2006, pp. 118-123.
-
(2006)
Design Automation and Test in Europe (DATE)
, pp. 118-123
-
-
Murali, S.1
Coenen, M.2
Radulescu, A.3
Goossens, K.4
De Micheli, G.5
-
11
-
-
0344119476
-
Efficient Synthesis of Networks on Chip, in
-
A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Efficient Synthesis of Networks on Chip", in ICCD, 2003, pp. 146-150.
-
(2003)
ICCD
, pp. 146-150
-
-
Pinto, A.1
Carloni, L.P.2
Sangiovanni-Vincentelli, A.L.3
-
13
-
-
36349012734
-
A Detailed Architectural-level Power Model for Router Buffers, Crossbars and Arbiters
-
Technical report, Princeton University
-
H. Wang, "A Detailed Architectural-level Power Model for Router Buffers, Crossbars and Arbiters", Technical report, Princeton University, 2004.
-
(2004)
-
-
Wang, H.1
-
14
-
-
84948976085
-
Orion: A Power-Performance Simulator for Interconnection Networks
-
Turkey
-
H. Wang, X. Zhu, L. Peh and S. Malik, "Orion: A Power-Performance Simulator for Interconnection Networks", 35th International Symposium on Microarchitecture (MICRO), Turkey, 2002.
-
(2002)
35th International Symposium on Microarchitecture (MICRO)
-
-
Wang, H.1
Zhu, X.2
Peh, L.3
Malik, S.4
-
17
-
-
27144481574
-
-
G.Ascia, V. Catania, and M Palesi, An Evolutionary Approach to Network-on-Chip Mapping Problem, in The IEEE Congress on Evolutionary Computation, 2005, pp.112-119.
-
G.Ascia, V. Catania, and M Palesi, "An Evolutionary Approach to Network-on-Chip Mapping Problem," in The IEEE Congress on Evolutionary Computation, 2005, pp.112-119.
-
-
-
-
18
-
-
33746590812
-
Linear Programming Based Techniques for Synthesis of Network-on-Chip Achitectures
-
K. Srinvasan, K. Chatha, and G. Konjevod "Linear Programming Based Techniques for Synthesis of Network-on-Chip Achitectures", IEEE Tran. on VLSI, Vol. 14, No. 4, 2006, pp. 407-420.
-
(2006)
IEEE Tran. on VLSI
, vol.14
, Issue.4
, pp. 407-420
-
-
Srinvasan, K.1
Chatha, K.2
Konjevod, G.3
-
19
-
-
51849152734
-
NoC link analysis under power and performance constraints
-
Greece
-
M. Kim, D. Kim, and E. Sobelman, "NoC link analysis under power and performance constraints" ISCAS, Greece, 2006.
-
(2006)
ISCAS
-
-
Kim, M.1
Kim, D.2
Sobelman, E.3
|