NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 265-270

  Chan, Jeremy ^a   Parameswaran, Sri ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARTS COMPUTING; BENCHMARKING; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC LOAD FORECASTING; ELECTRIC NETWORK TOPOLOGY; ENERGY POLICY; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUITS; ITERATIVE METHODS; MICROPROCESSOR CHIPS; PACKET NETWORKS; ROUTERS; ROUTING ALGORITHMS; TOPOLOGY;

COMMUNICATION GRAPHS; COMMUNICATION PARADIGMS; DESIGN AUTOMATION CONFERENCE; DESIGN SPACES; FLOORPLANNER; HOP-COUNT; HYBRID NETWORKS; ITERATIVE DESIGNS; ITERATIVE IMPROVEMENTS; LOWER ENERGIES; MIN-CUT; NETWORK LATENCIES; NETWORKS-ON-CHIP; NOC SYNTHESIS; ON-CHIP NETWORKS; OPTIMIZED APPLICATION; PACKET-SWITCHED; PACKET-SWITCHED NETWORKS; POINT-TO-POINT NETWORKS; REAL-WORLD; SOUTH PACIFIC; STATE OF THE ARTS; SYSTEM LEVELS; SYSTEM ON CHIPS; TEST CASES; TOPOLOGY GENERATION; TRAFFIC PATTERNS; WIRE LENGTHS;

SWITCHING CIRCUITS;

EID: 49549119939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4483953     Document Type: Conference Paper

References (20)

1. S. N. Adya and I. L. Markov. Fixed-outline floorplanning : Enabling hierarchical design. IEEE Trans. on VLSI, 2003.
2. T. Ahonen, D. A. Sigenza-Tortosa, H. Bin, and J. Nurmi. Topology optimization for application-specific networks-on-chip. In SLIP, 2004.
3. J. Castro and N. Nabona. An implementation of linear and nonlinear multicommodity network flows. European Journal of Operational Research, 1996.
4. J. Chan and S. Parameswaran. NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. In VLSI Design, 2004.
5. J. Chan and S. Parameswaran. NoCEE: energy macro-model extraction methodology for network on chip routers. In ICCAD, pages 254-259, 2005.
6. T. F. Chan, J. Cong, J. R. Shinnerl, K. Sze, and M. Xie. mPL6: enhanced multilevel mixed-size placement. In ISPD, 2006.
7. J. Hu, Y. Deng, and R. Marculescu. System-level point-to-point communication synthesis using floorplanning information. In ASP-DAC/VLSI, January 2002.
8. J. Hu and R. Marculescu. Energy-aware mapping for tile-based noc architectures under performance constraints. In ASP-DAC, January 2003.
9. Y. Hu et al. Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization. In ICCD, 2005.
10. G. Karypis and V. Kumar. Multilevel k -way hypergraph partitioning. In DAC, 1999.
11. S. Murali et al. Designing application-specific networks on chip with floorplan information. In ICCAD, 2006.
12. S. Murali and G. D. Micheli. SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs. In DAC, pages 914-919, 2004.
13. Ü. Y. Ogras and R. Marculescu. Application-specific network-on-chip architecture customization via long-range link insertion. In ICCAD, pages 246-253, 2005.
14. A. Pinto, L. Carloni, and A. Sangiovanni-Vincentelli. Synthesis of on-chip interconnection structures: From point-to-point links to networks-on-chip. Technical Report UCB/EECS-2006-147, UC Berkeley, 2006.
15. A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli. Efficient synthesis of networks on chip. In ICCD, 2003.
16. J. A. Roy, S. N. Adya, D. A. Papa, and I. L. Markov. Min-cut floorplacement. IEEE Trans. on CAD, 25(7):1313-1326, July 2006.
17. K. Srinivasan and K. S. Chatha. A low complexity heuristic for design of custom network-on-chip architectures. In DATE, 2006.
18. K. Srinivasan, K. S. Chatha, and G. Konjevod. Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. In ICCD, 2004.
19. K. Srinivasan, K. S. Chatha, and G. Konjevod. Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. VLSI Syst., 2006.
20. D. Starobinski, M. Karpovsky, and L. A. Zakrevski. Application of network calculus to general topologies using turn-prohibition. IEEE/ACM Trans. Netw., 2003.