Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias

Journal of Micromechanics and Microengineering

Volumn 21, Issue 8, 2011, Pages

  Kühne, Stéphane ^a   Hierold, Christofer ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DIRECT BOND; DIRECT BONDING; DIRECT INTEGRATION; ELECTRICAL INTERCONNECTS; FABRICATED DEVICE; HYBRID BONDING; INTERCONNECT METALLIZATION; INTERCONNECTION TECHNOLOGY; INTERFACIAL VOIDS; LOW TEMPERATURE WAFER BONDING; MEMSDEVICES; METALLIZATION LAYERS; PLANARIZATION; PROCESS FLOWS; THROUGH SILICON VIAS; TLP BONDING; TRANSIENT LIQUID PHASE BONDING; ULTRA-THIN; WAFER LEVEL PACKAGING; WAFER-LEVEL PACKAGING TECHNOLOGY;

CHIP SCALE PACKAGES; METALLIZING; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS;

WAFER BONDING;

EID: 79961219930     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/21/8/085032     Document Type: Article

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