Design, process development and prototyping of 3D packaging with multi-stacked flip chips and peripheral through silicon via interconnection

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2006, Pages 80-85

  Hon, Ronald ^a   Lee, S W Ricky ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BRAZING; CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; CONCEPTUAL DESIGN; COPPER; COPPER PLATING; DYNAMIC POSITIONING; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTROPLATING; LEAD; MICROELECTRONICS; MICROPROCESSOR CHIPS; NONMETALS; OPTICAL DESIGN; PERCOLATION (SOLID STATE); PROCESS DESIGN; PROCESS ENGINEERING; SILICON; SILICON WAFERS; SOLDERING; TECHNOLOGY; THREE DIMENSIONAL; WELDING;

3-D PACKAGING; DIE STACKING; ELECTRONICS MANUFACTURING; FLIP CHIPPING; INTERNATIONAL CONFERENCES; LEAD-FREE SOLDERING; PROCESS DEVELOPMENTS; PROTOTYPE DESIGNS; PROTOTYPING; SOLDER BALLS; SYSTEM-IN-PACKAGE; THREE-DIMENSIONAL PACKAGING; THROUGH SILICON VIA; THROUGH-SILICON VIAS; WAFER THINNING; WAFER-LEVEL FABRICATION;

ELECTRONICS PACKAGING;

EID: 34250816560     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMT.2006.4456436     Document Type: Conference Paper

References (8)

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3. th Symposium on Mechanics of SMT & Photonic Structures, ASME International Mechanical Engineering Congress & Exposition, Anaheim, California, U.S.A., November 13-20, 2004. (IMECE2004/62322 on CD-ROM)
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8. N. T. Nguyen, E. Boellaard, N. P. Pham, V. G. Kutchoukov, G. Craciun and P. M. Sarro, "Through-Wafer Copper Electroplating for Three-Dimensional Interconnects," Journal of Micromechanics & Microengineering, 2002 (12), pp. 395-399.