Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

Journal of Micromechanics and Microengineering

Volumn 17, Issue 6, 2007, Pages 1200-1205

  Lin, Chiung Wen ^a   Yang, Hsueh An ^a,b   Wang, Wei Chung ^a,b   Fang, Weileun ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; ELECTROPLATING; MEMS; MICROMACHINING; MICROSTRUCTURE; SILICON WAFERS; SURFACE MOUNT TECHNOLOGY;

MICROSYSTEM INTEGRATION; THROUGH-WAFER VIAS; WAFER-LEVEL PACKAGING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 34249662299     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/17/6/014     Document Type: Article

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