Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection

Microelectronics Reliability

Volumn 50, Issue 4, 2010, Pages 489-497

  Shen, Li Cheng ^a   Chien, Chien Wei ^a   Cheng, Hsien Chie ^b   Lin, Chia Te ^b  

^a Advanced Process Engineering   (Taiwan)

^b FENG CHIA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D INTERCONNECT; BONDING LAYERS; CAP STRUCTURE; CHIP BONDING; CHIP STACKING; CONDUCTIVE LAYER; FEASIBILITY STUDIES; FINITE ELEMENTS; INSULATION LAYERS; INTERCONNECT RELIABILITY; INTERCONNECTION TECHNOLOGY; INTERFACE QUALITY; LOW-COST LASERS; METAL CAP; METAL LAYER; NOVEL PROCESS; PHOTO PROCESS; SEED LAYER; SOLDER DIPPING; STRESS SIMULATIONS; STRUCTURAL SYMMETRY; THERMAL LOADINGS; THREE-DIMENSIONAL (3D); VIA FIRST; VIA INTERCONNECTION; VIA-HOLE; WAFER-LEVEL 3D INTEGRATION;

ELECTRONIC EQUIPMENT MANUFACTURE; METALS; SILICON WAFERS; STRESS ANALYSIS; TECHNOLOGY; THREE DIMENSIONAL; WAFER BONDING;

CHIP SCALE PACKAGES;

EID: 77950022517     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.10.012     Document Type: Article

References (15)

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