Through-wafer copper electroplating for three-dimensional interconnects

Journal of Micromechanics and Microengineering

Volumn 12, Issue 4, 2002, Pages 395-399

  Nguyen, N T ^a   Boellaard, E ^a   Pham, N P ^a   Kutchoukov, V G ^a   Carciun, G ^a   Sarro, P M ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANISOTROPY; ASPECT RATIO; COPPER; ELECTROPLATING; PHOTOLITHOGRAPHY; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PLASMA ETCHING; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SILICON WAFERS; THREE DIMENSIONAL;

INTERCONNECTS; THROUGH WAFER; TRENCH FILLING; WAFER THINNING;

ELECTRIC CONNECTORS;

EID: 0036646379     PISSN: 09601317     EISSN: None     Source Type: Journal    
DOI: 10.1088/0960-1317/12/4/308     Document Type: Article

References (8)

1. Overview and development trends in the field of MEMS packaging
2. Three-dimensional shared memory fabricated using wafer stacking technology
3. The 3-D computer
4. A micromachining post-process module for RF silicon technology
5. Ultra-low resistance, through-wafer via (TWV) technology and its applications in three dimensional structures on silicon
6. High density electrical feedthrough fabricated by deep reactive ion etching of pyrex glass
7. Copper electroplating for integrated RF-devices
8. Aspect ratio and crystallographic orientation dependence in deep dry silicon etching at cryogenic temperatures