메뉴 건너뛰기




Volumn 51, Issue 5, 2011, Pages 914-918

NBTI reliability on high-k metal-gate SiGe transistor and circuit performances

Author keywords

[No Author keywords available]

Indexed keywords

CASCODE; CHANNEL CONTROL; CIRCUIT PERFORMANCE; EXPERIMENTAL DATA; INTERFACE STATE; METAL-GATE; MODEL PARAMETERS; MOSFETS; NEGATIVE BIAS TEMPERATURE INSTABILITY; OUTPUT POWER; P-MOSFETS; POWER-ADDED EFFICIENCY; RF-CIRCUITS;

EID: 79953663683     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.12.015     Document Type: Article
Times cited : (8)

References (25)
  • 1
    • 50249185641 scopus 로고    scopus 로고
    • A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging
    • K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, and M. Bost A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging Int Electron Dev Meet Tech Dig 2007 247 250
    • (2007) Int Electron Dev Meet Tech Dig , pp. 247-250
    • Mistry, K.1    Allen, C.2    Auth, C.3    Beattie, B.4    Bergstrom, D.5    Bost, M.6
  • 2
    • 77957902313 scopus 로고    scopus 로고
    • Reliability characterization of 32 nm high-k and metal-gate logic transistor technology
    • Pae S, Ashok A, Choi J, Ghani R, He J, Lee S-H, et al. Reliability characterization of 32 nm high-k and metal-gate logic transistor technology. In: Proc int reliab phys symp; 2010. p. 287-92.
    • (2010) Proc Int Reliab Phys Symp , pp. 287-292
    • Pae, S.1    Ashok, A.2    Choi, J.3    Ghani, R.4    He, J.5    Lee, S.-H.6
  • 5
    • 40549122135 scopus 로고    scopus 로고
    • Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation
    • DOI 10.1109/TED.2007.902883
    • A.E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M.A. Alam Recent issues in negative-bias temperature instability: initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation IEEE Trans Electron Dev 2007 2143 2154 (Pubitemid 351492059)
    • (2007) IEEE Transactions on Electron Devices , vol.54 , Issue.9 , pp. 2143-2154
    • Islam, A.E.1    Kufluoglu, H.2    Varghese, D.3    Mahapatra, S.4    Alam, M.A.5
  • 6
    • 40549121324 scopus 로고    scopus 로고
    • Defect generation in p-MOSFETs under negative-bias stress: An experimental perspective
    • S. Mahapatra, and M.A. Alam Defect generation in p-MOSFETs under negative-bias stress: an experimental perspective IEEE Trans Dev Mater Reliab 2008 35 46
    • (2008) IEEE Trans Dev Mater Reliab , pp. 35-46
    • Mahapatra, S.1    Alam, M.A.2
  • 8
    • 77954418524 scopus 로고    scopus 로고
    • Analysis of SRAM reliability under combined effect of NBTI, process and temperature variations in nano-scale CMOS
    • H. Singh, and H. Mahmoodi Analysis of SRAM reliability under combined effect of NBTI, process and temperature variations in nano-scale CMOS Int Conf Future Inform Technol 2010 1 4
    • (2010) Int Conf Future Inform Technol , pp. 1-4
    • Singh, H.1    Mahmoodi, H.2
  • 9
  • 13
  • 15
    • 1142304527 scopus 로고    scopus 로고
    • Mobility and performance enhancement in compressively strained SiGe channel pMOSFETs
    • Z. Shi, D. Onsongo, and S.K. Banerjee Mobility and performance enhancement in compressively strained SiGe channel pMOSFETs Appl Surf Sci 2004 248
    • (2004) Appl Surf Sci , pp. 248
    • Shi, Z.1    Onsongo, D.2    Banerjee, S.K.3
  • 16
    • 77950143676 scopus 로고    scopus 로고
    • Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si cap and high-k metal gate stacks
    • J.-W. Oh, P. Majhi, R. Jammy, R. Joe, A. Dip, and T. Sugawara Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si cap and high-k metal gate stacks VLSI Technol Syst Appl 2009 22 23
    • (2009) VLSI Technol Syst Appl , pp. 22-23
    • Oh, J.-W.1    Majhi, P.2    Jammy, R.3    Joe, R.4    Dip, A.5    Sugawara, T.6
  • 17
    • 33646043186 scopus 로고    scopus 로고
    • Impact of strained- Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs
    • G.K. Dalapati, S. Chattopadhyay, K.S.K. Kwa, S.H. Olsen, Y.L. Tsang, and R. Agaiby Impact of strained- Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs IEEE Trans Electron Dev May 2006 1142 1152
    • (2006) IEEE Trans Electron Dev , Issue.MAY , pp. 1142-1152
    • Dalapati, G.K.1    Chattopadhyay, S.2    Kwa, K.S.K.3    Olsen, S.H.4    Tsang, Y.L.5    Agaiby, R.6
  • 18
    • 79953665405 scopus 로고    scopus 로고
    • The impact of La-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress condition
    • Kang CY, Young CD, Huang J, Kirsch P, Heh D, Sivasubramani P, et al. The impact of La-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress condition. In: Proc int electron dev meet; 2008. p. 1-4.
    • (2008) Proc Int Electron Dev Meet , pp. 1-4
    • Kang, C.Y.1    Young, C.D.2    Huang, J.3    Kirsch, P.4    Heh, D.5    Sivasubramani, P.6
  • 19
    • 78049310308 scopus 로고    scopus 로고
    • Tradeoff between hot carrier and negative bias temperature degradations in high-performance Si1-x Gex pMOSFETs with high-k /metal gate stacks
    • W.-H. Choi, C.-Y. Kang, J.-W. Oh, B.-H. Lee, P. Majhi, and H.-M. Kwon Tradeoff between hot carrier and negative bias temperature degradations in high-performance Si1-x Gex pMOSFETs with high-k /metal gate stacks IEEE Electron Dev Lett November 2010 1211 1213
    • (2010) IEEE Electron Dev Lett , Issue.NOVEMBER , pp. 1211-1213
    • Choi, W.-H.1    Kang, C.-Y.2    Oh, J.-W.3    Lee, B.-H.4    Majhi, P.5    Kwon, H.-M.6
  • 21
    • 64549141904 scopus 로고    scopus 로고
    • Comprehensive understanding of surface roughness and Coulomb scattering mobility in biaxially-strained Si MOSFETs
    • Zhao Y, Takenaka M, Takagi S. Comprehensive understanding of surface roughness and Coulomb scattering mobility in biaxially-strained Si MOSFETs. In: Proc int Electron Dev Meet; 2008. p. 1-4.
    • (2008) Proc Int Electron Dev Meet , pp. 1-4
    • Zhao, Y.1    Takenaka, M.2    Takagi, S.3
  • 22
    • 79953656787 scopus 로고    scopus 로고
    • http://www.agilent.com/find/eesof-ads
  • 25
    • 50549089988 scopus 로고    scopus 로고
    • CMOS RF design for reliability using adaptive gate-source biasing
    • J.S. Yuan, and H. Tang CMOS RF design for reliability using adaptive gate-source biasing IEEE Trans Electron Dev 2008 2348 2353
    • (2008) IEEE Trans Electron Dev , pp. 2348-2353
    • Yuan, J.S.1    Tang, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.