|
Volumn , Issue , 2008, Pages 440-443
|
Impact of NBTI on the performance of 35nm CMOS digital circuits
|
Author keywords
Degradation; Inverters; Negative bias temperature instability (NBTI); SRAM; Static noise margin
|
Indexed keywords
CMOS DIGITAL CIRCUITS;
CMOS INVERTERS;
DEVICE PHYSICS;
INVERTERS;
LONG TERMS;
MOS FETS;
NANO-SCALE DEVICES;
NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI);
POWER DISSIPATIONS;
POWER-SUPPLY VOLTAGES;
SRAM;
STATIC NOISE MARGIN;
DEGRADATION;
DIGITAL INTEGRATED CIRCUITS;
ELECTRIC POWER UTILIZATION;
INTEGRATED CIRCUITS;
MOSFET DEVICES;
NANOTECHNOLOGY;
NEGATIVE TEMPERATURE COEFFICIENT;
STATIC RANDOM ACCESS STORAGE;
THERMODYNAMIC STABILITY;
|
EID: 60749127044
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ICSICT.2008.4734569 Document Type: Conference Paper |
Times cited : (7)
|
References (22)
|