Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si cap and high-k metal gate stacks

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2009, Pages 22-23

  Oh, Jungwoo ^a   Majhi, Prashant ^a   Jammy, Raj ^a   Joe, Raymond ^b   Dip, Anthony ^b   Sugawara, Takuya ^b   Akasaka, Yasushi ^b   Kaitsuka, Takanobu ^b   Arikado, Tsunetoshi ^b   Tomoyasu, Masayuki ^b  

^a SEMATECH   (United States)

^b TOKYO ELECTRON LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

C-V HYSTERESIS; GATE CONTROL; GATE STACKS; GATE-LEAKAGE CURRENT; HIGH MOBILITY; HIGH QUALITY; HIGH-K GATE DIELECTRICS; INTERFACE TRAP DENSITY; METAL GATE STACK; MOBILITY ENHANCEMENT; OFF-STATE CURRENT; OFF-STATE CURRENT REDUCTION; P-MOSFETS; POTENTIAL BARRIERS; SI (100) SUBSTRATE; SI-GE FILMS; SIGE CHANNELS; SMALL BANDGAP;

ENERGY GAP; EPITAXIAL FILMS; GATE DIELECTRICS; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES; SECURITY SYSTEMS; SILICON; SILICON ALLOYS;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 77950143676     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2009.5159274     Document Type: Conference Paper

References (2)

1. P.Zimmerman et al., IEDM, p.655, 2006.
2. O.Weber et al., IEDM, p.143, 2005.