Tradeoff between hot carrier and negative bias temperature degradations in high-performance Si1 - XGex pMOSFETs with high-κ/metal gate stacks

IEEE Electron Device Letters

Volumn 31, Issue 11, 2010, Pages 1211-1213

  Choi, Won Ho ^a,b   Kang, Chang Young ^a   Oh, Jung Woo ^a   Lee, Byoung Hun ^c   Majhi, Prashant ^a   Kwon, Hyuk Min ^a   Jammy, Raj ^a   Lee, Ga Won ^b   Lee, Hi Deok ^b  

^a SEMATECH   (United States)

^b Chungnam National University   (South Korea)

^c Gwangju Institute of Science and Technology (GIST)   (South Korea)

Author keywords

channel hot carrier (CHC); Charge trapping; negative bias temperature instability (NBTI); pMOSFET; SiGe

Indexed keywords

BAND GAPS; BARRIER HEIGHTS; CHANNEL HOT CARRIERS; DIELECTRIC INTERFACE; GE CONCENTRATIONS; METAL GATE STACK; NEGATIVE BIAS; NEGATIVE BIAS TEMPERATURE INSTABILITY; P-MOSFETS; PMOSFET; SIGE;

CHARGE TRAPPING; CONCENTRATION (PROCESS); GERMANIUM; HOT CARRIERS; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; SILICON; SILICON ALLOYS; THERMODYNAMIC STABILITY;

DEGRADATION;

EID: 78049310308     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2071851     Document Type: Article

References (19)

1. P. Majhi, P. Kalra, R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B.J. Cho, S. Banerjee, W. Tsai, H. Tseng, and R. Jammy, "Demonstration of high-performance PMOSFETs using Si-SixGe1\-x-Si quantum wells with high-k/metal-gate stacks," IEEE Electron Device Lett., vol. 29, no. 1, pp. 99-101, Jan. 2008.
2. M.-L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, "Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 97, no. 1, pp. 011101(1)-011101(27), Jan. 2005.
3. x /Si p-MOSFETs with high-k/metal gate," in VLSISymp. Tech. Dig., 2008, pp. 56-57.
4. T. Krishnamohan, D. H. Kim, C. Jungemann, Y Nishi, and K. C. Sarawat, "Strained-Si, relaxed-Ge or strained-(Si)Ge for future nanoscaled p-MOSFETs?" in VLSI Symp. Tech. Dig., 2006, pp. 144-145.
5. x/Si quantum wells with high-k/metal gate stacks and additive uniaxial strain for 22 nm technology node," in IEDM Tech. Dig., 2007, pp. 727-730.
6. M. A. Quevedo-Lopez, S. A. Krishnan, D. Kirsch, C. H. J. Li, J. H. Sim, C. Huffman, J. J. Peterson, B. H. Lee, G. Pant, B. E. Gnade, M. J. Kim, R. M. Wallace, D. Guo, H. Bu, and T. P. Ma, "High performance gate first HfSiON dielectric satisfying 45 nm node requirements," in IEDM Tech. Dig., 2005, pp. 437-440.
7. K. Takahashi, K. Manabe, A. Morioka, T. Ikarashi, T. Yoshihara, H. Watanabe, and T. Tatsumi, "High mobility dual metal gate MOS transistors with high-k gate dielectrics," in Proc. Int. Conf. Solid State Devices Mater., 2004, pp. 22-23.
8. G. Bersuker, P. Zeitzoff, G. A. Brown, and H. R. Huff, "Dielectrics for future transistors," Mater. Today, vol. 7, no. 1, pp. 26-33, Jan. 2004.
9. B. H. Lee, R. Choi, J. H. Sim, S. A. Krishnan, J. J. Peterson, G. A. Brown, and G. Bersuker, "Validity of constant voltage stress based reliability assessment of high-k devices," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 20-25, Mar. 2005.
10. G. Ribes, J. Mitard, M. Denais, S. Bruyere, F Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on high-k dielectrics reliability issues," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 5-19, Mar. 2005.
11. E. P. Gusev and C. P. D'Emic, "Charge detrapping in HfO2 high-k gate dielectric stacks," Appl. Phys. Lett., vol. 83, no. 25, pp. 5223-5225, Dec. 2003.
12. K. T. Lee, C. Y Kang, O. S. Yoo, R. Choi, B. H. Lee, J. C. Lee, H. D. Lee, and Y H. Jeong, "PBTI-associated high-temperature hot carrier degradation of nMOSFETs with metal-gate/high-k dielectrics," IEEE Electron Device Lett., vol. 29, no. 4, pp. 389-391, Apr. 2008.
13. T. Irisawa, T. Numata, N. Sugiyama, and S. Takagi, "On the origin of increase in substrate current and impact ionization efficiency in strained-Si n-and p-MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 993-998, May 2005.
14. D. Maji, F Crupi, E. Amat, E. Simoen, B. De Jaeger, D. P. Brunco, C. R. Manoj, V R. Rao, P. Magnone, G. Giusi, C. Pace, L. Pantisano, J. Mitard, R. Rodríguez, and M. Nafría, "Understanding and optimization of hot-carrier reliability in Germanium-on-Silicon pMOSFETs," IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1063-1069, May 2009.
15. C. G Ahn, H. S. Kang, Y K. Kwon, and B. K. Kang, "Effects of segregated Ge on electrical properties of SiO2 /SiGe interface," Jpn. J. Appl. Phys., vol. 37, no. 3B, pp. 1316-1319, Mar. 1998.
16. D. K. Schroeder and J. A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, no. 1, pp. 1-18, Jul. 2003.
17. y substrates," Appl. Phys. Lett., vol. 48, no. 8, pp. 538-540, Feb. 1986.
18. S. A. Krishnan, M. Q. Lopez, H.-J. Li, P. Kirsch, R. Choi, C. Young, J. J. Peterson, B. H. Lee, G. Bersuker, and J. C. Lee, "Impact of nitrogen on PBTI characteristics of HfSiON/TiN gate stacks," in Proc. Int. Rel. Phys. Symp., 2006, pp. 325-328.
19. S. Mahapatra, V D. Maheta, A. E. Islam, and M. A. Alam, "Isolation of NBTI Stress generated interface trap and hole-trapping components in PNO p-MOSFETs," IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 236-242, Feb. 2009.