Analysis of SRAM reliability under combined effect of NBTI, process and temperature variations in nano-scale CMOS

2010 5th International Conference on Future Information Technology, FutureTech 2010 - Proceedings

Volumn , Issue , 2010, Pages

  Singh, Harwinder ^a   Mahmoodi, Hamid ^a  

^a SAN FRANCISCO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; ACCESS TIME; AGING EFFECTS; AGING PHENOMENA; BIASED TEMPERATURE INSTABILITIES; CMOS TECHNOLOGY; COMBINED EFFECT; DEVICE PERFORMANCE; FAULTY CELLS; HIGHER TEMPERATURES; LIMITING FACTORS; MOS-FET; NANO SCALE; RELIABILITY PROBLEMS; STATIC RANDOM ACCESS MEMORY; TEMPERATURE VARIATION; TRAPPED CHARGE; WORST CASE;

CMOS INTEGRATED CIRCUITS; DEGRADATION; INFORMATION TECHNOLOGY; MOS DEVICES; NANOSTRUCTURED MATERIALS; RELIABILITY ANALYSIS; TEMPERATURE DISTRIBUTION; THRESHOLD VOLTAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 77954418524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FUTURETECH.2010.5482682     Document Type: Conference Paper

References (8)

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2. Rakesh Vattikonda, Wenping Wang, Yu Cao," Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design" inDesign Automation Conference, July 2006.
3. B. C. Paul, et. al., "Impact of NBTI on the Temporal Performance degradation of digital circuits," IEEE Electron Device Letters, vol.26, no.8, Aug 2005.
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6. Kunhyuk Kang et. al., "Chracterization of NBTI induced Temporal Performance Degradation in Nano-Scale SRAM array using IDDQ,"International Test Conference, pp. 1-10, Oct. 2007.
7. Yangang Wang et. al., "Impact of NBTI on the Performance of 35nm CMOS Digital Circuits," International Conference on Solid-State and Integrated-Circuit Technology, pp. 440-443, Oct. 2008.
8. Sanjay V. Kumar et. al., "Impact of NBTI on SRAM Read Stability and Design for Reliability" International Symposium on Quality Electronic Design, pp. 216-218, March 2006.