Penelope: The NBTI-aware processor

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 85-96

  Abella, Jaume ^a   Vera, Xavier ^a   González, Antonio ^a  

^a Intel Research Cambridge Lab   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

GENERIC STRATEGIES; GLOBAL STRATEGIES; HIGH TEMPERATURE (HT); INDIVIDUAL (PSS 544-7); INTERNATIONAL SYMPOSIUM; LOGIC INPUTS; MAXIMUM OPERATING FREQUENCY (FMAX); MICRO ARCHITECTURES; NEGATIVE BIAS- TEMPERATURE-INSTABILITY (NBTI); PENELOPE; PMOS TRANSISTORS; STORAGE STRUCTURES; SUPPLY VOLTAGES;

ATOMIC PHYSICS; ATOMS; DEGRADATION; ENERGY STORAGE; MOSFET DEVICES; SULFATE MINERALS; THERMODYNAMIC STABILITY; TRANSISTORS;

NEGATIVE TEMPERATURE COEFFICIENT;

EID: 47349086635     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.11     Document Type: Conference Paper

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