Reliability characterization of 32nm high-K and metal-gate logic transistor technology

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 287-292

  Pae, Sangwoo ^a   Ashok, Ashwin ^a   Choi, Jingyoo ^a   Ghani, Tahir ^a   He, Jun ^a   Lee, Seok Hee ^a   Lemay, Karen ^a   Liu, Mark ^a   Lu, Ryan ^a   Packan, Paul ^a   Parker, Chris ^a   Purser, Richard ^a   Amour, Anthony St ^a   Woolery, Bruce ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Burn in; Component; High k dielectrics; Metal gate transistor; Process charging; TDDB and BTI

Indexed keywords

BURN-IN; COMPONENT; HIGH-K DIELECTRICS; METAL-GATE TRANSISTOR; PROCESS CHARGING; TDDB AND BTI;

GATE DIELECTRICS; METALS; TRANSISTORS;

RELIABILITY;

EID: 77957902313     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488814     Document Type: Conference Paper

References (9)

1. 2 SRAM Cell Size in a 291Mb Array," in IEDM Tech. Dig., 2008.
2. nd Generation High-K + Metal Gate Transistors," in IEDM Tech. Dig., 2009, pp. 659-662.
3. S. Pae et al., "Characterization of SILC and Its End-of-Life Reliability Assessment on 45nm High-K and Metal-Gate Technology," in International Reliability Physics Symp. Proc., 2009, pp. 499-504.
4. 2-based high-k gate dielectrics," in IEDM Tech. Dig., 2004, pp. 129-132.
5. S. Pae et al., "BTI reliability of 45 nm high-K + metal-gate process technology," in International Reliability Physics Symp. Proc., 2008, pp. 352-357.
6. S. Ramey et al., "Frequency and recovery effects in high-k BTI degradation," in International Reliability Physics Symp. Proc., 2009, pp. 1023-1027.
7. M. Alavi et al., "Effect of MOS device scaling on process induced gate charging," in Plasma Process-Induced Damage Symp. Proc., 1997, pp. 7-10.
8. R. Kasim et al., "Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging," in International Reliability Physics Symp. Proc., 2009, pp. 350-354.
9. B. Kaczer et al., "Impact of gate-oxide breakdown of varying hardness on narrow and wide nFET's," in International Reliability Physics Symp. Proc., 2004, pp. 79-83.