Inserting data encoding techniques into NoC-based systems

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 299-304

  Palma, José C S ^a   Indrusiak, Leandro Soares ^b   Moraes, Fernando G ^c   Ortiz, Alberto Garcia ^b   Glesner, Manfred ^b   Reis, Ricardo A L ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^c PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DECODING; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; MATHEMATICAL MODELS;

DATA ENCODING TECHNIQUES; NETWORKS-ON-CHIP; NOC-BASED SYSTEMS; TRANSITION ACTIVITY;

SIGNAL ENCODING;

EID: 36349035909     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.58     Document Type: Conference Paper

References (14)

1. A. Iyer and D. Marculescu. "Power and performance evaluation of globally asynchronous locally synchronous processors". 29th Annual International Symposium on Computer Architecture (ISCA), pp. 158-168, May 2002.
2. W. Dally and B. Towles. "Route packets, not wires: on-chip interconnection networks". Design Automation Conference (DAC), pp. 684-689, June 2001.
3. Burd. T and Brodersen, R. "Energy Efficient Microprocessor Design". Kluwer Academic Publishers, 2002. Pages: 376.
4. M. Pedram. "Power minimization in IC design". ACM Trans. Design Automat. Electron. Syst., vol. 1, no. 1, Jan. 1996.
5. th Symposium on Integrated Circuits and Systems Design -SBCCI 2005. New York: ACM Press, 2005. pp. 196-201.
6. F. Moraes, N. Calazans, A. Mello, L. Möller and L. Ost. "HERMES: an infrastructure for low area overhead packet-switching networks on chip". The VLSI Journal Integration, vol. 38, issue 1, pp. 69-93, October 2004.
7. L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi. "Architecture and Synthesis Algorithms for Power-Efficient Bus Interfaces". Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 19, Issue 9, Sept. 2000 Page(s):969-980.
8. M. R. Stan, W. P. Burleson. "Bus-Invert Coding for Low-Power I/O". VLSI Systems, IEEE Transactions on Volume 3, Issue 1, March 1995 Page(s):49-58.
9. H. Mehta, R. M. Owens, M. J. Irwin. "Some Issues in Gray Code Addressing". GLS-VLSI-96, pp. 178-180, Mar. 1996.
10. Ramos, P.; Oliveira, A. "Low Overhead Encodings for Reduced Activity in Data and Address Buses". Em Proceedings of the International Symposium on Signals, Circuits and Systems, pp. 21-24. Julho, 1999.
11. L. Ost, A. Mello; J. Palma, F. Moraes, N. Calazans. "MAIA - A Framework for Networks on Chip Generation and Verification". ASP-DAC, Jan. 2005.
12. Bjerregaard, T.; Mahadevan, S. "A survey of research and practices of Network-on-chip". ACM Computing Surveys, v.38(1), 2006, pp. 1-51.
13. C. Brooks, E.A. Lee, X. Liu, S. Neuendorffer, Y. Zhao, H. Zheng. "Heterogeneous Concurrent Modeling and Design in Java (Volume 1: Introduction to Ptolemy II,") Technical Memorandum UCB/ERL M05/21, University of California, Berkeley, CA USA 94720, July 15, 2005.
14. Sylvester, D.; Chenming Wu; "Analytical modeling and characterization of deep-submicrometer interconnect". Proceedings of the IEEE. Volume 89, Issue 5, May 2001 Page(s):634-664.