A power and energy exploration of network-on-chip architectures

Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip

Volumn , Issue , 2007, Pages 163-172

  Banerjee, Arnab ^a   Mullins, Robert ^a   Moore, Simon ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKGATING; ENERGY EXPLORATION; NETWORK CONGESTION; NETWORK-ON-CHIP ARCHITECTURES; STATE POWER;

CMOS INTEGRATED CIRCUITS; CONGESTION CONTROL (COMMUNICATION); MATHEMATICAL MODELS; ROUTERS;

MICROPROCESSOR CHIPS;

EID: 36349006382     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.6c     Document Type: Conference Paper

References (11)

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