Low-Overhead error detection for networks-on-Chip

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 219-224

  Berman, Amit ^a   Keidar, Idit ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

DECODER CIRCUITS; DECODING PROCESS; DEEP SUB-MICRON; DETECTION LEVELS; INTERCONNECT RELIABILITY; LOW COMPLEXITY; NETWORK ON CHIP; NETWORKS ON CHIPS; NOVEL METHODS; PARITY BITS; PATH DIVERSITY; POWER SAVINGS; REDUNDANT INFORMATIONS; SHORTEST PATH ROUTING;

ASYMPTOTIC ANALYSIS; DECODING; VLSI CIRCUITS; WIRELESS SENSOR NETWORKS;

ERROR DETECTION;

EID: 77950989466     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413150     Document Type: Conference Paper

References (11)

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