A low power approach to system level pipelined interconnect design

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2004, Pages 45-52

  Chandra, Vikas ^a   Xu, Anthony ^a   Schmit, Herman ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Low Power; Pipelined Interconnect; Voltage Scaling

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA PROCESSING; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; FLOW CONTROL; MATHEMATICAL MODELS;

DATA RATES; LOW POWER; PIPELINED INTERCONNECT; VOLTAGE SCALINGS;

INTEGRATED CIRCUIT LAYOUT;

EID: 19544378160     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/966747.966757     Document Type: Conference Paper

References (20)

1. I. F. Akyildiz, "Mean Value Analysis for Blocking Queueing Networks," IEEE Transactions on Software Engineering, 1988.
2. L. Benini, G. De Micheli, "Network on Chips: A New SoC Paradigm," IEEE Computer, 2002.
3. M. T. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," Proceedings of IEDM, 1995.
4. L. P. Carloni, K. L. McMillan, A. Saldanha and A. L. Sangiovanni-Vincentelli, "A Methodology for Correct-by-Construction Latency Insensitive Design," IEEE International Conference on Computer-Aided Design (ICCAD), 1999.
5. V. Chandra, A. Xu, H. Schmit and L. Pileggi, "An Interconnect Channel Design Methodology for High Performance Integrated Circuits," IEEE Design Automation and Test in Europe (DATE), 2004.
6. V. Chandra, G. Carpenter and J. Burns, "Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs," IEEE International Conference on Computer Design (ICCD), 2003.
7. T. Chelcea and S. M. Nowick, "A Low-Latency FIFO for Mixed-Clock Systems," International Workshop on VLSI, 2000.
8. P. Cocchini, "Concurrent Flip-Flop and Repeater Insertion for High Performance Integrated Circuits," IEEE International Conference on Computer-Aided Design (ICCAD), 2002.
9. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," IEEE Design Automation Conference, June 2001.
10. S. Hassoun and C. J. Alpert, "Optimal Path Routing in Single- and Multiple-clock Domain Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003.
11. R. Ho, K. W. Mai and M. Horowitz, "The Future of Wires," Proceedings of the IEEE, April 2001.
12. T. Ishihara and K. Asada, "A System Level Memory Power Optimization Technique using Multiple Supply and Threshold Voltages," IEEE Design Automation Conference, 2001.
13. A. Iyer and D. Marculescu, "Power Efficiency of Voltage Scaling in Multiple Clock, Multiple Voltage Cores," IEEE International Conference on Computer-Aided Design (ICCAD), 2002.
14. J. Kao, S. Narendra and A. Chandrakasan, "Sub-threshold Leakage Modeling and Reduction Techniques," IEEE International Conference on Computer-Aided Design (ICCAD), 2002.
15. T. Lin and L. Pileggi, "Throughput-Driven IC Communication Fabric Synthesis," IEEE International Conference on Computer-Aided Design (ICCAD), 2002.
16. T. Lin, "Ph.D. work in Progress," Dept. of ECE, Carnegie Mellon University, USA.
17. D. Manjunath et. al., "QNAT: A Graphical Tool for the Analysis of Queueing Networks," IEEE TENCON Intl. Conference, 1998.
18. K. Nowka et al, "A 32-bit PowerPC System-on-a-chip with Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling," IEEE Journal of Solid-State Circuits, 2002.
19. G. Semeraro et al, "Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling," High Performance Computer Architecture, 2002.
20. D. Sylvester and K. Keutzer, "Getting to the Bottom of Deep Sub-micron," IEEE International Conference on Computer-Aided Design (ICCAD), 1998.