Accurate energy dissipation and thermal modeling for nanometer-scale buses

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 51-60

  Sundaresan, Krishnan ^a   Mahapatra, Nihar R ^a  

^a Michigan State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN STAGE; POWER DISSIPATION; TECHNOLOGY SCALING; WORKLOADS;

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC LOADS; ELECTRIC WIRE; HEATING; MATHEMATICAL MODELS;

ENERGY DISSIPATION;

EID: 28444490698     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.5     Document Type: Conference Paper

References (20)

1. K. Banerjee. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues (Invited Paper). In Proceedings of the Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference, pages 38-50, Mar. 2001.
2. K. Banerjee and A. Mehrotra. Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. In Proceedings of the International Conference on Computer-Aided Design, pages 158-164, 2001.
3. K. Banerjee and A. Mehrotra. Global Interconnect Warming. IEEE Circuits and Devices, pages 16-32, Sept. 2001.
4. J. Cantin and M. Hill. Cache Performance for SPEC CPU2000 Benchmarks. URL: http://www.cs.wisc.edu/multifacet/misc/spec2000cachedata/, 2003.
5. T.-Y. Chiang, K. Banerjee, and K. Saraswat. Compact Modeling and SPICE-based Simulation for Electrothermal Analysis of Multilevel ULSI Inteconnects. In Proceedings of the International Conference on Computer-Aided Design, pages 165-172, 2001.
6. T.-Y. Chiang and K. Saraswat. Closed-form Analytical Thermal Model for Accurate Temperature Estimation of Multilevel ULSI Interconnects. In 2003 Symposium on VLSI Circuits Digest of Papers, pages 275-279, 2003.
7. B. Cmelik and D. Keppel. SHADE: A Fast Instruction-Set Simulator for Execution Profiling. ACM SIGMETRICS Performance Evaluation Review, 22(1): 128-137, May 1994.
8. W. Huang, M. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact Thermal Modeling for Temperature-Aware Design. In Proceedings of the Annual ACM/IEEE Design Automation Conference, June 2004.
9. K. Kim, K. Back, N. Shanbhag, C. Liu, and S. Kang. Coupling-driven signal encoding scheme for low-power interface design. In Proceedings of the International Conference on Computer-Aided Design, pages 318-321, Nov. 2000.
10. M. Mui, K. Banerjee, and A. Mehrotra. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth, and Power Dissipation. IEEE Transactions on Electron Devices, 51(3): 195-203, Feb. 2004.
11. K. Nabors, S. Kim, J. White, and S. Senturia. Fast Capacitance Extraction of General Three-Dimensional Structures. In Proceedings of International Conference on Computer Design, pages 479-484, 1991.
12. A. Naeemi, R. Venkatesan, and J. D. Meindl. Optimal Global Interconnects for GSI. IEEE Transactions on Electron Devices, 50(4):980-987, Apr. 2003.
13. J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits, Second edition. Prentice-Hall, Dec. 2002.
14. Semiconductor Industry Association. International Technology Roadmap for Semiconductors (ITRS), 2001 Edition, 2001.
15. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankara-narayanan, and D. Tarjan. Temperature-Aware Microarchitecture. In Proceedings of the 30th International Symposium on Computer Architecture, June 2003.
16. P. Sotiriadis and A. Chandrakasan. Bus Energy Minimization by Transition Pattern Coding (TPC) Using a Detailed Deep Sub-micron Bus Model. In Proceedings of the International Conference on Computer-Aided Design, 2001.
17. P. Sotiriadis and A. Chandrakasan. A Bus Energy Model for Deep Submicron Technology. IEEE Transactions on VLSI Systems, 10(3):341-350, June 2002.
18. M. Stan and W. Burleson. Bus-Invert Coding for Low-Power I/O. IEEE Transactions on VLSI Systems, 3:49-58, Mar. 1995.
19. W. Ye, N. Vijaykrishnan, M. Kandemir, and M.J.Irwin. The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool. In Proceedings of the Annual ACM/IEEE Design Automation Conference, pages 340-345, June 2000.
20. Y. Zhang, J. Lach, K. Skadron, and M. Stan. Odd/even Bus Invert with Two-Phase Transfer for Buses with Coupling. In Proceedings of International Symposium on Low Power Electronics and Design, pages 80-83, Aug. 2002.